Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
help for this special model	fencl_xu	1	2051	Jan 22^nd, 2010, 5:42am By: Geoffrey_Coram
Using analogLib components with verilog-AMS	immcinto	3	3930	Jan 19^th, 2010, 10:37am By: Andrew Beckett
odd behavior with trasition filter in Verilog-A / HSPICE	bobr	2	2283	Jan 19^th, 2010, 5:44am By: Ari
Setting voltage in "static" analysis, in keeping it in transient analysis	Ari	2	1952	Jan 19^th, 2010, 5:40am By: Ari
Import VHDL test bench in Virtuoso AMS	fran2k5	3	4598	Jan 16^th, 2010, 8:07am By: Andrew Beckett
verilogA model of fully differential opamp	Dipankar	1	5221	Jan 8^th, 2010, 8:59am By: sheldon
error while simulating using AMS in cadence	bharath	3	2525	Jan 2^nd, 2010, 5:55pm By: Peruzzi
order of calculation last_crossing() and cross()	Ari	3	2732	Dec 23^rd, 2009, 7:34am By: Geoffrey_Coram
$random, $arandom and repeatability across simulators	Ari	1	1623	Dec 18^th, 2009, 7:17am By: Geoffrey_Coram
how to perform multiple assignments on case statement	Ari	2	4087	Dec 16^th, 2009, 1:46pm By: Ari
[Error] Strange char in source text (ASCII (96))	michele bergo	2	2794	Dec 15^th, 2009, 4:34am By: michele bergo
Regarding data type in verilogA	somisetty	5	8628	Dec 11^th, 2009, 5:16pm By: Ken Kundert
random time delay	jdac_18	1	2216	Dec 10^th, 2009, 10:56am By: Ken Kundert
verilog-AMS	sree 4all	5	256	Dec 8^th, 2009, 2:10am By: somisetty
Need level-shifter Verilog-A code	awg	0	432	Dec 3^rd, 2009, 12:41pm By: awg
bsim in verilog-A	acabe	2	4559	Dec 2^nd, 2009, 8:28am By: acabe
verilogA code of 8-bit shift registers	somisetty	0	2634	Nov 30^th, 2009, 10:01pm By: somisetty
For statement condition error?	sylak	8	236	Nov 30^th, 2009, 3:52pm By: Geoffrey_Coram
need a Verilog-A sampling and hold model wihout hidden state	fantaci	1	2041	Nov 27^th, 2009, 4:40am By: pancho_hideboo
Can VerilogA code co-simulate with C or script languages?	couragebo	9	8268	Nov 25^th, 2009, 1:56am By: couragebo

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