Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
What is the strict definition of a "compact model" ?	engelbrl	2	2491	Jul 1^st, 2009, 2:44pm By: engelbrl
Testbench Verilog AMS	brenox	1	2608	Jun 29^th, 2009, 11:55am By: Geoffrey_Coram
PFD verilog-A model question	sch	1	3596	Jun 24^th, 2009, 10:52am By: Geoffrey_Coram
Verilog-A/MS	Dracon	9	7451	Jun 24^th, 2009, 4:44am By: pancho_hideboo
What happens if a Verilog always statement is re-triggered before it finishes?	ViggoBiggo	4	3964	Jun 23^rd, 2009, 2:55pm By: ViggoBiggo
How to generate Verilog-A model for a programmable divider?	lois	4	6396	Jun 23^rd, 2009, 1:59pm By: jbdavid
Verilog-A opamp	Dracon	1	3767	Jun 17^th, 2009, 1:25am By: flz
issue betwen blocking and no blocking	idriss	0	1093	Jun 15^th, 2009, 8:48am By: idriss
noise_table question in the phase domain model of VCO	lily	2	2413	Jun 9^th, 2009, 4:50am By: pancho_hideboo
Interpreting input logic busses as signed integers	Alexander E�wein	3	2828	Jun 2^nd, 2009, 4:04am By: Alexander E�wein
current source definition	kanan	2	2490	May 19^th, 2009, 7:06am By: Ken Kundert
VerlogA, AHDL, VerilogAMS	casual (Ex Member)	2	2667	May 15^th, 2009, 5:36pm By: casualzone - Ex Member
ideal transformer modelling	tarullim	1	2175	May 14^th, 2009, 7:03am By: Geoffrey_Coram
CUVDNF: Could not determine discipline	makelo	3	6766	May 1^st, 2009, 5:29am By: Andrew Beckett
Clock state	nishant22	1	1828	Apr 27^th, 2009, 8:30am By: Peruzzi
Problem with the timer event	Rooney	5	4126	Apr 23^rd, 2009, 9:45am By: Ken Kundert
AMS modeling of thermal noise in IUS62	fet	3	2936	Apr 20^th, 2009, 9:29am By: fet
how to write a verilogA code to generate a voltage source?	liletian	5	1607	Apr 17^th, 2009, 5:36pm By: patrick
digital output signal generation	kanan	3	2878	Apr 17^th, 2009, 7:46am By: Peruzzi
AES	SUBU	2	2222	Apr 12^th, 2009, 8:52am By: Andrew Beckett

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