Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
phase wrapping, either 1 or 0 in VCO	saralandry	0	1284	Feb 5^th, 2016, 7:32pm By: saralandry
multiple I/O with one pin in verilog A	saralandry	0	1198	Feb 5^th, 2016, 7:11pm By: saralandry
Two VerilogA files output data with different frequency. Why?	Jacki	3	3373	Feb 1^st, 2016, 11:43pm By: Jacki
Creating two pulses with different rise times using two transition operators	Rosh	1	1460	Feb 1^st, 2016, 10:48am By: Ken Kundert
Output for a pulse is just a DC voltage. Help!	Rosh	2	2143	Jan 29^th, 2016, 10:55am By: Geoffrey_Coram
trancision filter warning in verilogA	deltasigmaADC	2	2952	Jan 28^th, 2016, 9:48pm By: deltasigmaADC
*How to read a .log file into VerilogA?**	Jacki	6	4497	Jan 25^th, 2016, 11:35pm By: Jacki
AMS Errors in Sacle Factor (P=10e+15)	frozenduck	3	787	Jan 20^th, 2016, 2:53pm By: frozenduck
How do I generate the following voltage profile?	Rosh	1	1670	Jan 20^th, 2016, 8:05am By: Geoffrey_Coram
Problem of transition delay used in DTC verilog-A model	Hamlee	12	235	Jan 14^th, 2016, 5:20am By: Geoffrey_Coram
Hierarchical current probing in Verilog-AMS with $cds_iprobe	gerhard_l	3	4560	Jan 14^th, 2016, 5:15am By: Geoffrey_Coram
the problem of AMS code for capacitor	eeBismarck	1	1862	Jan 5^th, 2016, 6:29am By: Geoffrey_Coram
ADPLL	HaAf	0	1245	Dec 18^th, 2015, 11:50am By: HaAf
Error launching ncvlog	dinac	3	4760	Nov 23^rd, 2015, 7:05am By: Joeyao Chou
Need some help with this code	wandola	1	2724	Nov 23^rd, 2015, 5:41am By: Torq
Tristate(hi z) PRBS source for 2-3 bits on the beginning	qalex	0	1317	Nov 11^th, 2015, 6:27am By: qalex
Consumption measurement	Torq	4	3158	Nov 5^th, 2015, 1:49am By: Torq
@cross event hitting zero exactly	Geoffrey_Coram	0	1151	Nov 2^nd, 2015, 8:05am By: Geoffrey_Coram
What does it mean by "S" as extrap_char of $table_model() ?	cheap_salary	1	1526	Nov 2^nd, 2015, 7:51am By: Geoffrey_Coram
$table_model($abstime, ...) is very slow in Cadence Spectre	cheap_salary	0	1584	Oct 30^th, 2015, 8:28am By: cheap_salary

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