Dear Ken, Andrew and all friends,
First of all, thanks for so detailed discussion about Pnoise on PFD/CP. But, there are still some unclear to me.
For example, the output frequency range of a PLL is 100MHz to 500MHz, the input frequency is 25MHz. Now, i would like to know the noise form CP. The Pnoise simulation is setup according to the above introduction. The input signals are the two pulses signal with an phase offset, which have the same frequency at 25MHz. The output is a grounded voltage source at the 0.5*Vdd. The simulation setup is shown as following:
Code: pss pss fund=25M harms=50 errpreset=liberal tstab=400n
+ saveinit=yes annotate=status
pnoise pnoise start=10 stop=10G maxsideband=50 oprobe=V3
+ annotate=status
...."
According the formal 56, 57 in the paper "jitter and phase" of Ken, we can calculate the jitter performance of CP.
My questions are:
1. How can I deside the integration range in formal 56 ?
In my CP, if the range is from 10Hz to 25MHz, the jitter=36p, while it is from 10Hz to 10G, the jitter = 76p. So the difference is too large.
2. Form the Pnoise of the CP, I have also a current peak at about 25MHz, which has been also mentioned by others. I think it is simliar to
http://www.designers-guide.org/Forum/?board=jitter;action=display;num=1129284499...In the Pnoise curve of my simulation, there is no a noise floor from f
c to Nosie Bandwith, which seems to confict with the figure 7 in paper. By the way, How can I know how large is Noise bandwidth for the CP? and, in Page 28 of the paper, "thus, the noise should be at least 40dB down and dropping at the highest frequency simulated." This is for phase noise(dBc/Hz) or for output noise (A**2/Hz)???
http://photo.163.com/openpic.php?user=zoujunjx&pid=500381664&_dir=%2F1744535...Any answer would be appreciated!