Ken Kundert
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The maximum frequency for the PSD is constrained to be fout/2. There is no way around that. However, you can increase fout. To do so you will need to pull at least part of the divider out of the VCO model. Currently, the VCO model models both the VCO and the divider. It does so to reduce the output frequency, which makes the model more efficient. In the example, the divide ratio is 10,000. If you pulled all of that out, the maximum frequency in the PSD would be 10,000 times higher, but the simulations would be 10,000 times more expensive. This might be viable if you switched to event-based modeling in Verilog-AMS or C. However, you can just pull out a fraction of 10,000, say a factor of 10. That would give you a higher upper bound on your PSD frequency, but would not make the simulation overly expensive (such that it requires a rewrite).
One generally does not need to make the maximum frequency for the PSD very high because once you get beyond the dynamics of the loop, the output noise response simply drops in proportion to 1/f2. This allows you to easily predict the high frequency phase noise performance from what you have. For example, in the paper Sphi(100kHz) = -45dBc. It will drop at a 20dB/dec rate, making it -105dBc at 100MHz.
-Ken
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