Anyone familiar with this?
I try to simulate the phase noise of a delay chain consisting of ECL-type (bipolar) inverters/limiting amplifiers. I have a number of such limiters, let's say 5 and I'm interested in the phase noise at the output of the chain. When I would follow the method described in the PLL-phase noise Design Guide, I would simulate one limiter's output noise with pNoise in the time domain at the zero crossing time of the output voltage wave form. (Simulation bench with this limiter loaded by another limiter). Then I would divide this noise voltage by the slope I get from PSS to convert the amplitude noise into phase noise as seen by the next limiter. To get the aggregate phase noise of the delay chain, I would add 10log(5) to the phase noise number, since there are 5 identical delay blocks in the chain, the slope at the output is similar, and I assume the different phase noise contributions are uncorrelated so they add up in power. This means we assume that no amplitude noise is transferred between consecutive blocks. I think that if it would be transferred, it would be amplified while phase noise is not.  Question: Is the assumption correct (no amplitude noise transfer)?  

So I simulated the noise at 30MHz offset from the 1st harmonic. Let's say the input frequency is 3GHz, then the noise at 3.030 GHz is what I looked at. I used maxsidebands=10 so a lot of folded down noise is contributing at that offset frequency.

This noise floor number results in -140.3dBc/Hz phase noise, and for 5 blocks it is theoretically (10log(5)) about 7dB higher, so -133.3dBc/Hz.  

I then tried to simulate the chain as a whole, using the same method but just looking at the amplitude noise at the output of the 5th limiter, and dividing that number by the slope. The resulting phase noise number is -126.4dBc/Hz which is 6.9dB higher than the theoretical number.  

Where does the difference come from? Which of the two numbers is most reliable? Does SpectreRF do a good job in converting the amplitude noise into phase noise in the consecutive limiting blocks, or can it only handle one such hard non-linearity at a time (what noise sims is concerned) ??

And an extra one: if I add a capacitively coupled limiter after this delay chain, the noise at 3GHz+ 1MHz-30MHz is LOWER at the output zero crossing then at the input of this added limiter. This has to be some amplitude noise filtering effect, because it shouldn't affect the phase noise already present. Simulator issue or real issue?



Thanks for your help

Performing the simulation of the entire chain together will be more accurate than performing the simulation of a single stage. I suspect that the results are so different between the two because you are using too few sidebands. Try simulating with many more sidebands.

Your question about the capacitively coupled limiter is a bit unclear. From your description it sounds as if you are basically looking at the same signal, but simply looking at noise in threshold crossings for a different threshold voltage. If this is the case, it is not surprising that the noise level would be different. The noise is cyclostationary, meaning that its power level varies, generally substantially, over the period.

Remember that the concept of amplitude and phase noise are modulation concepts, and they assume that the modulation is slow relative to the carrier. This model works well for oscillators as most of the phase noise is at low frequencies. However, with clock chains, the noise is broadband. This means that if you try to decompose the noise into its amplitude and phase components, things can get weird because amplitute and phase components are orthogonal only if the modulation bandwidth is much less than the carrier frequency. In other words, for rapidly varying modulations, the distinction between amplitude and phase becomes largely meaningless.

-Ken

Your intuition about the maximum frequency can be misleading because in a circuit simulator, the models are split into resisitive and capacitive pieces. The resistive pieces have infinite bandwidth and can occasionally generate high frequency signals that the simulator must properly handle but that you never see externally because it gets absorbed by the capacitive pieces. Whether this is important I don't know. The easiest way to find out is to simply keep increasing maxsidebands. However, realize that there is a point of diminishing returns: as you increase the number of sidebands the noise will keep increasing, though slowly, while the simulation time increases more rapidly. See Tables 1 & 2 in http://www.designers-guide.com/Analysis/sc-filters.pdf to get a feel for the tradeoff.

Also, realize that simulating the stages separately will never give the accuracy of simulating them together. Off hand, I can think of two reasons for the difference. First, the driving and loading environment of the gate is somewhat different when simulated alone. Second, this particular method of measuring jitter looks a the noise at one point on transitions, but is that the best point? Also, is one point enough? Clearly, the sensitivity of the noise from a previous stage decreases as the input voltage moves away from the point of maximum gain, but how sharp is the decrease? Presumably noise from around that point also affects the output. The effect of this is captured naturally by the simulator for all but the last stage in the simulation. Thus, when simulating 5 stages together you get 1/5^th the error that you get when you simulate the stages individually (though there is a simulation procedure you can use to substantially reduce this error).

-Ken

Forgot to post my findings (no time either). Using a number for maxsidebands a lot higher than I would have done "intuitively" the results of time-domain and the results obtained with the "sources" method by mixing down to baseband using an ideal mixer and looking at the same offset frequencies, come really close (.1 to .5dBc). I'm happy with that.
The thing to do is, as always: keep re-simulating with ever increasing values for maxsidebands until the difference between two results is smaller than the error you can live with (or, if you want you can do a real error estimation calculation on it).