See http://www.designers-guide.com/Analysis/PLLjitter.pdf. Particularly section 7.

Jitter Man

Thankyou All,
I have a few doubt, Initially I generated the jittery clock using verilogA and also refering through the paper mentioned, but the project I am working on has very high divide by ratio, for example If we have a clock of 27Mhz (jittery of 100ps) and divider by 27000 we get a clk output from the divider of 1Khz with jitter, This clk is applied as reference to my PFD, while I need to simulate for a longer duration of 150 - 200ms (milli-sec).
If I plot the eye diagram of the clk output(27Mhz) for smaller duration say 100us, the jitter is around 100ps, if I plot the same for a longer duration say 1ms, jitter is 1-1.2ns and for 100ms duration its too high.
What I require is a clk of 27MHz with jitter of around 100ps, even if i run the simulation for 100 or more milli sec. The jitter should be with in the range, If I am wrong please correct me.

Thanks and regards,
Srihari