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DC/DC Buck's Phase Margin analysis using spectre ? (Read 302 times)
Ken Kundert
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #15 - Jan 04th, 2005, 5:25pm
 
One should never cut the feedback loop, whether you are using PSS or not. It leads to both simulation problems and lousy results. It is much better to either use the stability analysis in Spectre or the techniques outlined in my book (Designer's Guide to Spice & Spectre, section 3.4.1 on characterizing feedback amplifiers).

-Ken
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Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #16 - Jan 4th, 2005, 11:43pm
 
You also might want to take another look at my reply #3 to this topic. That method does not cut the loop, so if your original circuit converges, the circuit with the PAC sources inserted should do so as well.

You can find an implementation of this method for AC analysis in LTspice (free, see http://www.linear.com/company/software.jsp) at http://groups.yahoo.com/group/LTspice/files/Examples/Educational/LoopGain_Probe/... (free registration required).
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Richard
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #17 - Jan 6th, 2005, 12:16am
 
Thanks Frank and Ken for your prompt reply.

Frank : I downloaded the LT files. Pardon my knowledge, I find that to determine the voltage loop gain and phase response, you just need a AC=1, DC=0 voltage source inserted in the loop. (e.g. at the output and input gate of unity feedback amplifier). Why do we need to determine the current gain and subsequently : (Gv*Gi-1)/(Gv+Gi+2) function ?

 I am running the DC/DC with just the voltage source (pac=1) inserted with PSS and PAC analysis, hopefully I have some good results soon.
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Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #18 - Jan 6th, 2005, 11:31pm
 
You need to determine both voltage and current gain in order to properly account for loading effects. See http://www.stanford.edu/class/ee214/handouts/h21_lecture15.pdf (and http://www.stanford.edu/class/ee214/handouts/h20_lecture14.pdf as background information) or the articles mentioned in the LTspice example.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #19 - Jan 9th, 2005, 2:05pm
 
Frank : Appreciate so much for the link & info. From the reading, I think if you need to take into account of comprehensive loading such as capacitive loading, the current gain measurement would be necessary. Anyway, it seems that the spectre still couldn't resolve to converge to a solution, error prompt : Zero diagonal found in Jacobian at `xextfet.8' and `xextfet.8'.

Eugene : Do you happen to know any good reading article on the design of oscillator ramp for the buck converter ? I couldn't find one, and I find it pretty important as it is part of the modulator loop gain. Undecided
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #20 - Jan 9th, 2005, 5:03pm
 
I assume you have a pwm converter with either straight voltage mode control or current mode control. In either case, the frequency of the ramp limits your loop gain crossover frequency and the amplitude of the ramp scales the overall loop gain. Furthermore, any glitches in the ramp can cause all sorts of stability problems. Straight voltage mode control is fairly simple. The loop gain is proportional to the inverse of the amplitude of the ramp.  Current mode control is more complex because you actually have two ramps: the same ramp you have for voltage control and in addition, a current compensation ramp to stabilize the current loop. I can recommand a few papers on current compensation but I am not sure they will be easy to find because they are somewhat old:

1. R.B Ridley, "A New Small-Signal Model for Current-Mode Control". Power Conversion and Intelligent Motion Conference proceedings, Oct. 16-19, 1989.

2. R.D. Middlebrook, "Topics in Multiple-Loop Regulators and Current-Mode Programming. IEEE Power Electronics Specialists Conference proceedings, June 26-29, 1989.

3. R.D. Middlebrook and S. Cuk. "Advances in Switched-mode Power Conversion". TESLAco.

You should find a wealth of papers on current mode control in the archives of the IEEE power electronics specialists conference.  I suspect most papers will be at least 10 years old.

As I re-read your question, it occurs to me that perhaps you are asking about circuit design, not systems design. There are many ways to generate a ramp. Most power control chips generate it internally. If you are designing the ramp circuitry yourself, you could try texts such as
Millman and Taub, "Pulse, digital, and switching waveforms". McGraw Hill. This is an older text based on bipolar transistors. Something similar for newer technologies may exist. The main thing to worry about is keeping the ramp clean. As I said before, any imperfection in the ramp will adversely affect performance.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #21 - Jan 9th, 2005, 6:43pm
 
Eugene,
 Thanks for your prompt and informative reply !  Wow  :o, I'm learning alot from this forum. Yes, other than the first ref, I couldn't get hold of the other two.
 No, I am still refering to the design of ramp for the voltage-mode @ system level. All I know is the modulator gain is 1/Vramp(p-p), like you mentioned. So it seems like smaller Vramp voltage, the higher the gain, but how small can it go before the noise overwhelms it, is 50mV reasonable? Also, other than stability, does Vramp impact other parameters such as line, load regulation ? Also, how should we pick the DC offset of the ramp ?
 Please list any reference, no matter how old, I'll try to search for them.
Thanks. Roll Eyes
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Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #22 - Jan 9th, 2005, 11:39pm
 
[quote author=richard88  link=1102534266/15#19 date=1105308316]Anyway, it seems that the spectre still couldn't resolve to converge to a solution, error prompt : Zero diagonal found in Jacobian at `xextfet.8' and `xextfet.8'.
[/quote]
Does your circuit converge without the additional PAC source? If so, you might want to contact Cadence support because that would seem like a bug to me.
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abs
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #23 - Jan 10th, 2005, 2:10am
 
Hi, do you try the circuit in
http://ieeexplore.ieee.org/xpl/abs_free.jsp?arNumber=900125
it has a simple circuit with RC feedback.

Have you try pac for the DC/DC buck?
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #24 - Jan 10th, 2005, 10:30am
 
jws : Yes, I used PSS & PAC for analysis.

FInally, I have some results but I have to set the PSS option to traponly for the integration method instead of gear2only (usually this is recommended right ?)
Can anyone explain why traponly works in this case ?
Thanks. Smiley
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #25 - Jan 10th, 2005, 12:13pm
 
Richard88,
As you mentioned, the ramp should be large enough to overwhelm noise at that node.  By "noise", I don't just mean stochastic signals. I include deterministic interference such as diode reverse recovery transients that may effectively sneak into the ramp signal. Yes, a larger ramp will reduce loop gain, but I would think you could easily make that up in the error amplifier, as long as the "noise" is not coming through the error amplifier.  Neglecting noise for now, I believe the ramp only affects closed loop performance through the loop gain. So as I said, if you must use a large ramp I think you can make it up somewhere else in the loop. 50mV seems small to me but I've been away from power electronics for a few years. As for DC offset, I would align it with the output of the error amplifier to maximize the maximum dynamic range of the feedback loop if possible.

I don't remember any references specifically on voltage mode ramp design. Sorry. However, a state space averaged model should make quick simulation work of any study you need to perform to study the ramp Smiley
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abs
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #26 - Jan 10th, 2005, 6:53pm
 
Hi,Richard88
   you can adjust several other parameters for pss.
Would you give me a copy of you netlist. I can try it for
you. If the pac loop gain you got is the same as the LTspice.
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #27 - Jan 13th, 2005, 2:11am
 
Hi, Eugene
    Have you compare the results of spice state space averaged model and the spectreRF
result for DC/DC buck. If there are some different? Do you think which is more accurate?
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #28 - Jan 13th, 2005, 9:06am
 
Jws,

I have always wanted to apply SpectreRF to power electronics but never had the chance to complete the job. I was more or less dragged kicking and screaming from power electronics into RF. I've done state space averaging and used SpectreRF (for RF circuits). I expect SpectreRF to be more accurate than state space averaging. I would not be surprised if SpectreRF could simulate the closed loop response to glitches in the voltage and/or current compensation ramps if one could model the sneak path accurately. However, I do not think SpectreRF makes state space averaging obsolete. Unlike SpectreRF, state space averaging can give you closed form expressions for all the transfer functions of interest. Such closed form expressions can give the designer insight that can save him/her hundreds of SpectreRF simulations. Also, if you want to simulate high level control functions you may want to add VerilogA models that have hidden state. Last I heard, SpectreRF can't handle hidden state. I would use state space average models during the early phases of the design then check the design with SpectreRF. I would also use SpectreRF for bottom up analysis. In short, SpectreRF should be more accurate than state space averaging but I absolutely do not consider it a replacement for state space averaging.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #29 - Jan 14th, 2005, 10:31am
 
Eugene,
 I have got some results from spectre in running some simple examples of buck dc/dc, the results seems to be okay. It seems to be also modelling the delay through the digital driver driving the power switches which can be critical in performing closed loop response, as the extra pole from the delay might just cause the system to be unstable. I really wish there are more people try out and compare notes. I think if there is an article (or even book) from using spectre on DC/DC converter, it should be well-received.  :)
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