Richard,

I list three references below. I am certain the first is out of print. I pick such books up at garage sales and used book stores. I don't know if the others are in print. All three are fairly involved. I don't think such rigor is necessary if you have a solid understanding of the Nyquist stability criterion (NSC). The NSC states that a SISO system is stable if the Nyquist plot encircles the (-1,0) point CCW once for every RHP pole in the open loop system. ("open" refers the SISO loop in question). The trick to assessing a multiloop system as a sequence of single loop systems is to start with a known number of RHP poles. If we start with all loops open, the system is guaranteed to have zero RHP poles. As [3] suggests, it is sometimes most convenient to start with the highest bandwidth loop. For a current mode converter, that would be the innermost loop, the current loop. With all loops open, assess the loop gain of the first loop. It's ok if the first loop is unstable as long as you remember how many times the Nyquist plot encircled the (-1,0) point in the CW direction. That number equals the number of RHP poles the system has with just the first loop closed. The NSC does not depend how the plant was constructed or how any RHP poles came about; we can apply the NSC to the second loop with the first loop closed and all the rest open. The same argument applies to the next loop, and the next, and so on. Again, the key is to keep track of the number of RHP poles you add or subtract as you close each loop. By construction, when we close the last loop, we know how many RHP poles the system has with all loops closed.

There are other methods better suited for evaluating relative stability, depending on the system architecture. For example, for the case of one converter driving another, if the source impedance remains far below the load impedance over all frequencies, each loop can be assessed independent of the other. However, I have often gained valuable insight into system stability by checking my alternate methods against the sequential loop closure method.

[1] John Truxal, "Automatic Feedback Control System Synthesis". McGraw HIll. 1955. Pages 147-150.

[2] P. K. Sinha, "Multivariable Control, An Introduction". Marcel Dekker Inc. 1984. Pages 584-592.

[3] J. M. Maciejowski, "Multivariable Feedback Design". Addison-Wesley Publishing Co. 1989. Pages 137-142.

Frank Wiedmann wrote on Sep 13^th, 2006, 11:55pm:


This link does not work anymore. The article can now be found at http://www.kenkundert.com/docs/cd2001-01.pdf.

By the definition of small signal, such signals will not affect the behavior of a circuit in a nonlinear fashion. As a result, they cannot pass through a thresholding input. It might be helpful to think about PSS/PAC as a two phase process, where the the circuit is linearized about the time varying operating point in the PSS phase and the small signal is applied in the PAC phase. As a result, the small signal cannot affect the time at which a cross function triggers. Also, if you have a comparator that switched from saturated low to saturated high between two time points, such that there is no time point in which the small signal would propagate from the input to the output, you would see no signal transmission in PAC.

-Ken

Ken,

Jason claims that PSS/PAC works for his switch mode power supply when he uses behavioral comparators but not behavioral logic devices. What is the difference?

Jason,

I assume the two cases you mention are both brute force models, i.e. neither is a state space averaged model. Right?

-Eugene

Ken, that makes complete sense & I assumed something like that was the case.  I suppose it is necesary to write new behavioral logic models that have a 'linear' transition region.  This is probably straightforward, but i don't cherish the thought of writing a new verilog-a logic library.  I wonder if this will slow down the simulation? (probably not a big deal for this application...).  I think with some new logic cells we will be up and running these simulations no problem.

eugene,
my simulation is not ss-average, it is just PSS/PAC on a mostly behavioral syncronous buck converter.  to make convergence easier we made sure to clamp critical nodes with diodes & added enough parasitic cap to make the circuit 'realistic'.  Other than that everything ran fine with a symmetric (naturally sampled) ramp modulator.  I ran into problems trying to implement a dead time control circuit with behavioral logic (now i think this is a completely solvable problem).

Jason

Which sideband are you using in your PAC analysis?

I wonder what would happen if you made the comparator transfer curve less steep (i.e. larger transition region).