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DC/DC Buck's Phase Margin analysis using spectre ? (Read 105105 times)
Ken Kundert
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #30 - Jan 14th, 2005, 1:06pm
 
Richard,
   I think you are on the leading edge. Consider writing something for those that follow.

-Ken
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #31 - Jan 14th, 2005, 2:00pm
 
Richard88,

Thanks for the information. In the past, I've included such delays in my state space averaged models by inserting a properly terminated transmission line. But I am curious about your simulation. Did you mean to say SpectreRF instead of Spectre? If that is true and you are simulating digital circuitry, are you modeling the digital parts at the device or gate level or are you using VerilogA? If you are using VerilogA and SpectreRF, have you encountered a hidden state problem? How is your run time and how big is your circuit?
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #32 - Jan 15th, 2005, 11:27am
 
For those circuits that I'm running now, it seems not much different in results between using just Gv or (Gv*Gi-1)/(Gv+Gi+2) function, anyone came across similiar stuff ?
Also, I have run on one circuit, using the method of just Gv (and also the whole Gv, Gi function), the result is major different at about 50MHz onwards compared to using the "Low-pass filter" loop-cutter method, not sure which one to trust (the results from the loop-cutter seems more decent).

Thanks. Smiley
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« Last Edit: Jan 15th, 2005, 12:57pm by richard88 »  
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Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #33 - Jan 16th, 2005, 11:41pm
 
You probably have put your probe in a place in your circuit where Gi is very large. As can easily be seen, the result of the formula is very close to Gv in this case.

Personally, I would not trust the result of any loop gain simulation method that breaks the loop. There are just too many places where you can make an error when setting it up.
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #34 - Jan 17th, 2005, 8:27am
 
What is the switching frequency of your converter? If it's on the order of a few MHz or less, from a loop gain standpoint I don't think you should care about what happens at 50MHz. Your loop should cross over way below that and remain low. If the switching frequency was way below 50MHz and there was something interesting at 50MHz, I would analyze 50MHz performance with open loop models, perhaps one for each switch position.  Or, I might perform a closed loop simulation just to compute the steady state duty cycle, then drive the switch with that duty cycle in an open loop fashion to study 50MHz.

If you broke the loop with a voltage source at a point where the downstream impedance is much higher than the upstream impedance, I don't think you'd see much difference when you corrected for loading.  I would expect the difference to show up only at very high frequencies, frequencies where the impedances start to approach and possible cross each other.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #35 - Jan 21st, 2005, 12:13pm
 
Thanks for the reply, Frank and Eugene.
I keep trying a few more sims, and actually realized that (perhaps) the gain, phase response starts to have "spectrum replica" at switching frequency (1MHz....the clock), so I guess that's why you have those.... just wonder if there is a way to get rid of those nasty "noise"... Smiley
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #36 - Jan 21st, 2005, 7:52pm
 
Hi richard88,

For switch mode power supplies, small signal pertubations about the steady state conditions can be modeled by a continuous time system with a sampler at the switch. (Look for an 80s paper by Billy Lau and Dr. Middlebrook. I think Marty Schlect's book may also have a chapter on sampled data models of power converters.) If you break the loop right after the sampler, indeed you will see a periodic transfer function and must resort to z-domain stability theory... keep the poles inside the unit circle.  However, if you break the loop at a continuous time node, you should not see a periodic transfer function because the loop should have a low pass nature. If at the continuous time node you see a loop gain with magnitude anywhere near unity past 1/10 the switching frequency, you are almost certainly asking for stability problems.

Note that in most sampled data control systems, the sampler is followed by a DAC, which is mathematically a sample and hold. I this case, there is no sample and hold. There is only the power supply filter.

The replicated spectra you see could be real and if they are, you should probably reduce your cross over frequency, either by reducing gain, lowering the corner frequency of your filter, and/or changing your compensation.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #37 - Jan 22nd, 2005, 8:20pm
 
Thanks Eugene for the insightful analysis.

[  However, if you break the loop at a continuous time node, you should not see a periodic transfer function because the loop should have a low pass nature.

**I break at the resistor feedback (to the error amp). I think this should be okay. I still think there should be a periodic function, even at the output or the resistor feedback point, because you can see the voltage ripple of clock freq.

If at the continuous time node you see a loop gain with magnitude anywhere near unity past 1/10 the switching frequency, you are almost certainly asking for stability problems.

Note that in most sampled data control systems, the sampler is followed by a DAC, which is mathematically a sample and hold. I this case, there is no sample and hold. There is only the power supply filter.

The replicated spectra you see could be real and if they are, you should probably reduce your cross over frequency, either by reducing gain, lowering the corner frequency of your filter, and/or changing your compensation. [/quote]

**I get to know that the entire loop bandwidth has to be smaller than the clock freq, but didn't know it has to be 1/10......so if fclk=1MHz, the fbw<100kHz, is there any theory or intuitive reasoning behind this (especially like you mentioned the stability issue).  :)

Also, could you recommend any classic papers on the "digital gate-delay induced poles " or modelling of delay.
Thanks.
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #38 - Jan 23rd, 2005, 9:00pm
 
Richard88,

1) If you break your loop at the error amplifier (which is an continuous time node), I agree that you may see a bump at the switching frequency but I do not think you will see a periodic transfer function. The filter should attenuate higher harmonics more than lower harmonics. In my opinion, you see ripple at that node not because there is an instability but because the system is time varying, it's driven by a fixed clock operating at the ripple frequency.

2) Crossing the loop below 1/10 the switching frequency...This is a rule of thumb. 1/20 would be even better if you can afford it. If you violate this rule, you had better be have ultra-accurate components and a sampled-data model that accurately models all delays...and you had better now those delays accurately. The point I'm trying to make is that component tolerances, temperature drifts, and un-modeled effects (like delays) usually punish those who violate the rule.

3) The references below may not directly help you but they may give you some ideas. Sorry they are so old. As I said before, my power electroncis experience is from a previous life; I've been out of the field for 8 years now so my library is somewhat out of date. There may be newer and better papers out by now.

1. Daniel Mitchell, "Pulsewidth Modulator Phase Shift", IEEE Transactions on Aerospace and Electronic Systems, AES 16 No. 3, pp 272-278, May 1980.

2. W. M. Polivka, P.R.K. Chetty, and R.D. Middlebrook, "State Space Averaged Modeling of Converters with Parasitic and Storage-Time Modulation", IEEE Power Electronics Specialists Conference, 1980 Record, pp119-143.

3. R.D. Middlebrook and Slobodan Cuk, "Advances in Switched-Mode Power Conversion. Chapter 15. Predicting Modulator Phase Lag in PWM Converter Feedback Loops. TeslaCo.
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #39 - Sep 8th, 2006, 8:05pm
 
I am sorry but can anyone guide me on how you can break the loop for a current mode dcdc converter to see it's stability as I am dealing with a project on it? An example or any help will be grateful.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #40 - Sep 13th, 2006, 7:59am
 
fantusox wrote on Sep 8th, 2006, 8:05pm:
I am sorry but can anyone guide me on how you can break the loop for a current mode dcdc converter to see it's stability as I am dealing with a project on it? An example or any help will be grateful.


current mode typically has two loops : main feedback and inductor current sense loop. To check the stability I would think that you should break the main feedback loop just like voltage mode.
I am not so sure about using pss to analyse the current mode as the inductor current sense waveform can be large signal and not sure if it can be analysed accurately. I would love to hear any comments.

Richard

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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #41 - Sep 13th, 2006, 9:07am
 
I don't know of anyone who has fully demonstrated that PSS/PAC reliably computes the loop gain of a DC/DC converter. However, if you are using state space averaged models, you can compute the loop gain with AC analysis. If you want to break the current loop of a current mode converter, you will need to correct operating point, which means you will need a closed voltage loop too. If you insert your AC source (to break the loop) just before the DC/DC transformer, you break both loops. However, if you want to look at the current loop with the voltage loop opened in the AC sense, I don't know how to avoid using the larger inductor/capactor trick that everyone says is a bad ideal. I could be wrong, but I think Spectre's AC analysis is designed specifically for single loop systems.

In a multiloop system, it is often helpful to use a "sequential loop closure" procedure to assess stability. In the procedure, you examine the loops one at a time, usually from innermost to outermost. You start with all loops opened in the AC sense. After you assess a loop, you close it before assessing the next one. If you encounter an unstable inner loop, an outer loop can stabilize the system but to assess stability you must read the Nyquist criterion like a lawyer. A better way to assess stability would be to look at the closed loop poles. However, I have yet to see a very reliable pole/zero extraction tool for large circuits. Anyway, getting back to the sequential loop closure procedure, I'd be interested if someone knows of a better way to open the outer loops than to use large LC components.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #42 - Sep 13th, 2006, 11:35am
 
Eugene,
 I think without using large cap/ind to block the ac signal, the method is to use the stb (based on middlebrook's double null injection theorem) analysis in spectre. Essentially, if you break the loop at the input of error amp (assume infinite input impedance), you can place a voltage source in between with DC=0, AC=1, run the ac sim and plot the vout/vin to get the gain and phase plot.
 
 I have not read the Ridley's article which talk about small signal modelling of current mode converter. I would be interested to find out how the average model for modelling the two loops. I just find that with the inner loop which has inductor current waveform, to be compared at the comparator, seems to be a large signal behavior, which is not obvious for the model.

Richard

Eugene wrote on Sep 13th, 2006, 9:07am:
I don't know of anyone who has fully demonstrated that PSS/PAC reliably computes the loop gain of a DC/DC converter. However, if you are using state space averaged models, you can compute the loop gain with AC analysis. If you want to break the current loop of a current mode converter, you will need to correct operating point, which means you will need a closed voltage loop too. If you insert your AC source (to break the loop) just before the DC/DC transformer, you break both loops. However, if you want to look at the current loop with the voltage loop opened in the AC sense, I don't know how to avoid using the larger inductor/capactor trick that everyone says is a bad ideal. I could be wrong, but I think Spectre's AC analysis is designed specifically for single loop systems.

In a multiloop system, it is often helpful to use a "sequential loop closure" procedure to assess stability. In the procedure, you examine the loops one at a time, usually from innermost to outermost. You start with all loops opened in the AC sense. After you assess a loop, you close it before assessing the next one. If you encounter an unstable inner loop, an outer loop can stabilize the system but to assess stability you must read the Nyquist criterion like a lawyer. A better way to assess stability would be to look at the closed loop poles. However, I have yet to see a very reliable pole/zero extraction tool for large circuits. Anyway, getting back to the sequential loop closure procedure, I'd be interested if someone knows of a better way to open the outer loops than to use large LC components.

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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #43 - Sep 13th, 2006, 2:41pm
 
Hi Richard,

I have a rudimentary awareness of the stb probe (Middlebrook's method). My question is, does it work in general for a system that has multiple feedback loops?

I am certain you can use it on one loop while all other loops are closed. But to apply the Nyquist stability criterion, you must know how many RHP poles the other (closed) loops introduced. That requirement leads to the sequential loop closure method. The sequential loop closure method requires that you evaluate some loops with other loops opened. Does that mean we must break all loops with a stb probe? If so, how does Spectre know the sequence in which I want to assess the loops?

If each loop is assessed with all other loops closed, you will get the wrong answer. You can only use a sequential method by closing each loop only after it is assessed. If the stb probe really only works on one loop at a time, as I suspect, the sequential approach forces you to use large LC components to open the un-assessed loops without changing the DC operating point.

Many years ago, I used this method routinely on space craft power busses and motor control loops. Space craft power busses are powered by DC/DC converters and many of the loads are often DC/DC converters. Also, converters often use transformers to generate several output voltages, and those outputs are sometimes post regulated. Motor control loops often use current loops inside of position and/or velocity loops. All of these applications involve multiple feedback loops. The sequential loop closure approach has always given me answers consistent with transient simulations but I always had to use large LC components to apply the method. I'd love to avoid the LC components in a multiloop setting but I don't yet see how to do that.

-Eugene
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #44 - Sep 13th, 2006, 6:21pm
 
Eugene,
 As you said, the stb (I think) can only evaluate one loop.
 Infact, I didn't know about the sequential loop evaluation method when analysing multiple loop.
 I think this will be useful when dealing with linear regulator (LDO) when you have nested miller capacitor topology.
 Can you point a reference or show us how to do the sequential loop evaluation ?
Thanks,
Richard
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