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DC/DC Buck's Phase Margin analysis using spectre ? (Read 107363 times)
Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #45 - Sep 13th, 2006, 11:55pm
 
The stb analysis does not use Middlebrook's original method but an improved version of it, see http://www.thekunderts.net/ken/docs/c%26d2001-01.pdf. For a circuit with multiple loops, it can only be used if there is a critical wire that breaks all loops (see the article for details). The original reference for the sequential loop evaluation method is probably Bode's book "Network Analysis and Feedback Amplfier Design" (Reference 1 in the article).

For a better method to break multiple loops in Spectre, see Reply #14 of http://www.designers-guide.org/Forum/YaBB.pl?num=1155668476;start=all. However, you have to be aware that this is not quite the same as disabling the controlled sources of the active elements, which is what really would be required. Unfortunatly, transistor models usually do not give direct access to their internal controlled sources, so it is very difficult to apply this method in exactly the right way.
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #46 - Sep 14th, 2006, 12:01am
 
Richard,

I list three references below. I am certain the first is out of print. I pick such books up at garage sales and used book stores. I don't know if the others are in print. All three are fairly involved. I don't think such rigor is necessary if you have a solid understanding of the Nyquist stability criterion (NSC). The NSC states that a SISO system is stable if the Nyquist plot encircles the (-1,0) point CCW once for every RHP pole in the open loop system. ("open" refers the SISO loop in question). The trick to assessing a multiloop system as a sequence of single loop systems is to start with a known number of RHP poles. If we start with all loops open, the system is guaranteed to have zero RHP poles. As [3] suggests, it is sometimes most convenient to start with the highest bandwidth loop. For a current mode converter, that would be the innermost loop, the current loop. With all loops open, assess the loop gain of the first loop. It's ok if the first loop is unstable as long as you remember how many times the Nyquist plot encircled the (-1,0) point in the CW direction. That number equals the number of RHP poles the system has with just the first loop closed. The NSC does not depend how the plant was constructed or how any RHP poles came about; we can apply the NSC to the second loop with the first loop closed and all the rest open. The same argument applies to the next loop, and the next, and so on. Again, the key is to keep track of the number of RHP poles you add or subtract as you close each loop. By construction, when we close the last loop, we know how many RHP poles the system has with all loops closed.

There are other methods better suited for evaluating relative stability, depending on the system architecture. For example, for the case of one converter driving another, if the source impedance remains far below the load impedance over all frequencies, each loop can be assessed independent of the other. However, I have often gained valuable insight into system stability by checking my alternate methods against the sequential loop closure method.

[1] John Truxal, "Automatic Feedback Control System Synthesis". McGraw HIll. 1955. Pages 147-150.

[2] P. K. Sinha, "Multivariable Control, An Introduction". Marcel Dekker Inc. 1984. Pages 584-592.

[3] J. M. Maciejowski, "Multivariable Feedback Design". Addison-Wesley Publishing Co. 1989. Pages 137-142.
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richard88
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #47 - Oct 3rd, 2006, 10:34am
 
Eugene,
 Typically, in current mode control, we have the current loop much faster than the voltage loop and we can assume that the current loop is a closed one right ? Unless you are concerned with the stability of the current loop. I supose the current loop stability should be a simple one, why would there by RHP zero ?

Thanks,
Richard


Eugene wrote on Sep 13th, 2006, 2:41pm:
Hi Richard,

I have a rudimentary awareness of the stb probe (Middlebrook's method). My question is, does it work in general for a system that has multiple feedback loops?

I am certain you can use it on one loop while all other loops are closed. But to apply the Nyquist stability criterion, you must know how many RHP poles the other (closed) loops introduced. That requirement leads to the sequential loop closure method. The sequential loop closure method requires that you evaluate some loops with other loops opened. Does that mean we must break all loops with a stb probe? If so, how does Spectre know the sequence in which I want to assess the loops?

If each loop is assessed with all other loops closed, you will get the wrong answer. You can only use a sequential method by closing each loop only after it is assessed. If the stb probe really only works on one loop at a time, as I suspect, the sequential approach forces you to use large LC components to open the un-assessed loops without changing the DC operating point.

Many years ago, I used this method routinely on space craft power busses and motor control loops. Space craft power busses are powered by DC/DC converters and many of the loads are often DC/DC converters. Also, converters often use transformers to generate several output voltages, and those outputs are sometimes post regulated. Motor control loops often use current loops inside of position and/or velocity loops. All of these applications involve multiple feedback loops. The sequential loop closure approach has always given me answers consistent with transient simulations but I always had to use large LC components to apply the method. I'd love to avoid the LC components in a multiloop setting but I don't yet see how to do that.

-Eugene

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Frank Wiedmann
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #48 - Oct 4th, 2006, 12:49am
 
Frank Wiedmann wrote on Sep 13th, 2006, 11:55pm:
The stb analysis does not use Middlebrook's original method but an improved version of it, see http://www.thekunderts.net/ken/docs/c%26d2001-01.pdf.


This link does not work anymore. The article can now be found at http://www.kenkundert.com/docs/cd2001-01.pdf.
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Jason UCB
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #49 - Oct 6th, 2006, 4:43pm
 
I have a voltage-mode Buck PSS/PAC simulation that seems to work & gives correct small signal loop analysis ( a PSS/PAC loop analysis with double injection stability analysis).  I have not tried multi-loop (current mode), or any modulator that requires hidden-state blocks.
I have this problem:
PAC works fine for normal behavioral blocks (analogLib).  It also works fine for the ahdlLib comparator and real transistor level blocks.

When I place a verilogA (ahdlLib) logic block in the signal path, PAC fails.  The PAC output is zero regarless of the input.  There must be a solution for this?  Its strange because PSS works fine with v-a logic, i'm just not sure if i'm missing something that would solve the PAC problem.  Other than this i see no reason why you can't use PSS/PAC for switched mode power conversion.

Jason  
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Ken Kundert
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #50 - Oct 6th, 2006, 11:43pm
 
By the definition of small signal, such signals will not affect the behavior of a circuit in a nonlinear fashion. As a result, they cannot pass through a thresholding input. It might be helpful to think about PSS/PAC as a two phase process, where the the circuit is linearized about the time varying operating point in the PSS phase and the small signal is applied in the PAC phase. As a result, the small signal cannot affect the time at which a cross function triggers. Also, if you have a comparator that switched from saturated low to saturated high between two time points, such that there is no time point in which the small signal would propagate from the input to the output, you would see no signal transmission in PAC.

-Ken
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #51 - Oct 8th, 2006, 10:20pm
 
Richard,

Sorry for the late reply. I was out of town.

You are right about current mode control: the current loop is much faster than the voltage loop, it is easy to stabalize, and you can usually focus on the outer loop with the current loop closed. I meant to bring up multiple loops in a more general context (multiloop motor controls, post regulated power supplies, peak power tracking solar arrays with output voltage regulation).

-Eugene
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #52 - Oct 8th, 2006, 10:29pm
 
Ken,

Jason claims that PSS/PAC works for his switch mode power supply when he uses behavioral comparators but not behavioral logic devices. What is the difference?

Jason,

I assume the two cases you mention are both brute force models, i.e. neither is a state space averaged model. Right?

-Eugene

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Ken Kundert
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #53 - Oct 8th, 2006, 10:39pm
 
To get PAC to work on a behavoiral comparator model you need a transition region where the gain is finite, and the PSS analysis must put some points down in that region.

-Ken
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Jason UCB
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #54 - Oct 9th, 2006, 9:03am
 
Ken, that makes complete sense & I assumed something like that was the case.  I suppose it is necesary to write new behavioral logic models that have a 'linear' transition region.  This is probably straightforward, but i don't cherish the thought of writing a new verilog-a logic library.  I wonder if this will slow down the simulation? (probably not a big deal for this application...).  I think with some new logic cells we will be up and running these simulations no problem.

eugene,
my simulation is not ss-average, it is just PSS/PAC on a mostly behavioral syncronous buck converter.  to make convergence easier we made sure to clamp critical nodes with diodes & added enough parasitic cap to make the circuit 'realistic'.  Other than that everything ran fine with a symmetric (naturally sampled) ramp modulator.  I ran into problems trying to implement a dead time control circuit with behavioral logic (now i think this is a completely solvable problem).

Jason
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #55 - Oct 17th, 2006, 1:00pm
 
Some strange observations from PAC simulation:
I am now running a simple simulation with a ramp-comparator PWM followed by an inverter (see attached schematic).
Both the comparator and inverter have linear transition regions (based on tanh).  The comparator gain is high (10000), the inverter gain is 100.

I get strange results from PAC: the input signal is 1V as expected.  the output from the comparator (V1) is 1.43V (should be 1V?).  rest of voltages as follows:
Vin=1
V1=1.4
V2=3.4
Vout~6

According to my understanding, this circuit should have unity gain of the PAC fundamental.  This happens regardless of  accuracy settings of PSS.   especially strange that an RC network should have gain!

Any thoughts on this?  I can try to clarify if necesary - this is critical to getting PWM (i.e. switch-mode power supplies) to work.

jason
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #56 - Oct 17th, 2006, 10:31pm
 
Which sideband are you using in your PAC analysis?
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Jason UCB
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #57 - Oct 18th, 2006, 10:37am
 
I don't have it in front of me, but I believe it is the '0' sideband.  Whichever one corresponds to the fundamental of the PAC signal.  I definitely checked to make sure I am not looking at some strange harmonic.  my only guess is that this is related to the way PSS saves the steady state data - if there are discrete jumps in the PSS data could you end up with nonsensical gains from PAC?  the problem with this thought is that it doesn't seem to be related to the min timestep - I tried setting this to 100pS & still get strange results.
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Eugene
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #58 - Oct 18th, 2006, 4:49pm
 
I wonder what would happen if you made the comparator transfer curve less steep (i.e. larger transition region).
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Re: DC/DC Buck's Phase Margin analysis using spect
Reply #59 - Oct 18th, 2006, 5:32pm
 

Yes, i've tried playing with the gains of both the comparator and the inverter cells.  This does have an effect on the PAC results, but not in a rational way.  I'm using a gain of ~100 right now.
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