Ken,

The oscillator frequency is fo=4MHz. what I said was fo/2 = 2MHz.
The oscillator output is a square wave with a rise time from 100mV to 1.1V of 40pSec, therefore, the Slew Rate is indeed 1/40psec=20GV/sec.

No I did not multiply the period jitter by sqrt(fo*30us) yet. The reason I suspect 0.5fSec is too low because the current in each stage of my ring oscillator is very low. Its a low power design and therefore I am not optimisitic that my jitter will that good.

Thx

ic_engr

Ken,

I made some modifications to the ring oscillator design. I increased the current and maintained same frequency. When I run standard PSS and Pnoise simulation what I note is that the slope of the Phase noise plot is 30dB/decade upto near the fundamental freq. The fundamental is 4MHz.

The usual fc (1/f noise corner I used to see is now gone.

Can you help me understand what's happened.

Tx

ic_engr

This usually occurs because you set maxsidebands in the pnoise analysis to "0" - whereas it should be a number large enough to include all significant contributions. Setting it to 0 in particular will omit any up-converted flicker noise from DC, so that's often a cause.

Regards,

Andrew.

You might want to look at the noise contributions. I suspect that your noise may be dominated by the noise from the bias circuitry (I don't think that's necessarily unusual, if there's high gain from the bias circuitry to the output), and since that doesn't have any flicker noise, you don't see the flicker knee.

Can't remember if you're running in ADE - but if you are, use the noise contribution UI (under the results menu) to take a look at which devices contribute the most noise.

Regards,

Andrew.