I'm admittedly a novice in verilogA and am simply looking to define an input bus in the verilogA language.  For example, the verilogA 8-bit ADC in the ahdlLib library has 8 input terminals.  How does one convert this to a single 8-bit bus to reduce the terminal count on the symbol?

Thanks,

KP

NB: MOST people I have worked with have used the
0 bit as the LSB.. (and I like verilog 2001 syntax)
so
module myADC (input vin, clk, output [7:0] D);
electrical vin;
logic clk;
reg D;

always @(posedge clk) begin
// calculate the output code from V(vin);
end
endmodule.

For examples of a couple of ADC's and DAC's created this way look in the bmslib shipped with the cadence tools..
jbd