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VerilogA handling for buses (Read 11972 times)
kapylan_pallo
New Member
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Posts: 3
VerilogA handling for buses
Mar 29
th
, 2005, 10:02am
I'm admittedly a novice in verilogA and am simply looking to define an input bus in the verilogA language. For example, the verilogA 8-bit ADC in the ahdlLib library has 8 input terminals. How does one convert this to a single 8-bit bus to reduce the terminal count on the symbol?
Thanks,
KP
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gsuarez
Junior Member
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Posts: 11
Re: VerilogA handling for buses
Reply #1 -
Mar 30
th
, 2005, 12:03pm
I'm not an expert in Verilog-A but you can use this as an example,
module FLASH_ADC3bit(vin,vref,clk,dout);
input vin,vref,clk;
output [0:2] dout;
electrical vin,vref,clk;
electrical [0:2] dout;
George
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jbdavid
Community Fellow
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Posts: 378
Silicon Valley
Re: VerilogA handling for buses
Reply #2 -
Oct 2
nd
, 2005, 6:09pm
NB: MOST people I have worked with have used the
0 bit as the LSB.. (and I like verilog 2001 syntax)
so
module myADC (input vin, clk, output [7:0] D);
electrical vin;
logic clk;
reg D;
always @(posedge clk) begin
// calculate the output code from V(vin);
end
endmodule.
For examples of a couple of ADC's and DAC's created this way look in the bmslib shipped with the cadence tools..
jbd
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jbdavid
Mixed Signal Design Verification
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