Hi,
SpectreMDL probably won't help you either. It cannot really
alter the control flow as you wish here. It can stop a specific
transient prematurely when all measurements are complete
for that analysis, but you cannot conditionally run another
analysis based upon the result of a prior analysis, (ignoring
a search/optimization type loop).
Other than using Verilog-A, maybe the cleanest approach
would be to use the 'assert' statement to create your tests.
Then if the assert fails, it could exit without running any more
analyses. In the following example, you can define a
set of asserts, which generate an error upon failure. These
are then disabled for the following transient analysis. If
the assert(s) fail, the dc analysis will error out and then the
transient will not run. If they succeed, the transient will run
as expected.
// Define you assertions
assert1 assert dev=v1 param=i min=-25m level=error
// Run the DC
dc1 dc
// Disable the asserts for the transient analysis.
disableasserts checklimit disable=[ "assert1" ]
tran1 tran stop=1u
Best Regards,
John