Paul
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Savitha,
in fact you forgot to mention whether you were concerned about A/D conversion or D/A conversion. I guessed you were talking about ADCs, but maybe you can confirm this...
And as an addition to Ken's quite complete overview, I wanted to note that: - continuous-time ADCs are sensitive to clock jitter, which may be critical at high sampling rates. - multi-bit quantizers require mismatch-shaping (MMS) algorithms to keep the non-linearity low. Unfortunately MMS is not efficient at low OSR, which means that for RF ADCs, both the multi-bit approach and the high OSR approach are not very suitable. In that case, high-order single-bit topologies may be used, but are quite tricky to design due to the stability issues mentioned by Ken. An empirical study of high-order single-bit delta-sigma modulators Schreier, R., IEEE Transactions on Circuits and Systems II, Vol.40, Aug. 1993.
Paul
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