hello

I'm trying to model a mixed-signal mux4x1 which is digitally controlled. I really don't understand what I'm doing wrong in this model. I have a problem when it comes to the simulation. The error from the simulation log is as follows:

the following branches form a loop of rigid branches (shorts) when added to the circuit:

mux4x1_ana_tb V2:p (from mux4x1_ana_tb.x2 to ground)
mux4x1_ana_tb V4:p (from mux4x1_ana_tb.x0 to ground)
mux4x1_ana_tb V1:p (from mux4x1_ana_tb.x1 to ground)



I have 4 voltage sources as my inputs (nets x0 to x3), and a load resistance on the output.  I am also using an example of a switch from the Verilog AMS designers guide page 115, 3.2.1 . Here is the code that I am using:

module  MUX_ANALOG_2 ( OUT, IN0, IN1, IN2, IN3, SEL);

     //===================//
     // Ports Declaration //
     //===================//
     
     inout IN0, IN1, IN2, IN3;
     input [1:0] SEL;
     inout OUT;
     electrical OUT, IN0, IN1, IN2, IN3;
     
           
           
     //================//
     // Analog Process //
     //================//
     
     

           
     analog begin
           
           
           
                       
           if (SEL==2'b00) begin
                 V(OUT, IN0) <+ 0.0;
                 I(OUT, IN1) <+ 0.0;
                 I(OUT, IN2) <+ 0.0;
                 I(OUT, IN3) <+ 0.0;
           end else if (SEL==2'b01) begin
                 I(OUT, IN0) <+ 0.0;
                 V(OUT, IN1) <+ 0.0;
                 I(OUT, IN2) <+ 0.0;
                 I(OUT, IN3) <+ 0.0;
           end else if (SEL==2'b10) begin
                 I(OUT, IN0) <+ 0.0;
                 I(OUT, IN1) <+ 0.0;
                 V(OUT, IN2) <+ 0.0;
                 I(OUT, IN3) <+ 0.0;
           end else if (SEL==2'b11) begin
                 I(OUT, IN0) <+ 0.0;
                 I(OUT, IN1) <+ 0.0;
                 I(OUT, IN2) <+ 0.0;
                 V(OUT, IN3) <+ 0.0;
           end else begin
                 I(OUT, IN0) <+ 0.0;
                 I(OUT, IN1) <+ 0.0;
                 I(OUT, IN2) <+ 0.0;
                 I(OUT, IN3) <+ 0.0;
           end


     end

     


endmodule


What is the problem?  ???

The check for a loop of rigid branches gets a bit confused by complex switch branch structures. Now, if you're sure that there really isn't a loop (it looks like it), you can add an attribute before the analog block indicating that it should not do the check:

Code:

(* no_rigid_switch_branch *) analog begin
...
end 

We decided it was too difficult to make the check able to spot every possible loop, and so this was the solution that was created. You need to be using spectre from MMSIM60 for this attribute to be supported. Unfortunately the attribute is not yet supported in AMS Designer.

My Sourcelink solution 11021530 covers this in a bit more detail.

Regards,

Andrew.

Another trick I've sometimes used when dealing with switch branches is to declare both the V and I branches:

branch (a,int) br_rs;
branch (a,int) rs_short;

analog begin
 if (rs > 0)
   I(br_rs) <+ V(br_rs) / rs;
 else
   V(rs_short) <+ 0;

end