Arsenal_he,

  The Successive Approximation Algorithm is a binary search. After
sampling the input, you compare the input to half the full scale level. If
the input is greater than the reference level, you increment the MSB bit
of the Successive Approximation Register[SAR]. If not then the SAR
MSB bit is set to zero. The search continues from that point.

 Typically, twelve clock cycles would be required for a 10 bit SAR. Two
for sampling the input and 10 for performing the conversion. To meet
the speed requirement you my want to use non-linear clock periods. That
is make the sample and MSB clock periods longer and reduce the clock
periods for the LSB bits.

  The 8-channel requirement means that you have an 8-channel muliplexer
in front of the ADC so you can monitor multiple signals. This keeps cost
down in products, one ADC can perform many tasks.  

  In general, good design practices should allow you to meet the 10bit
rrequirement, however, the 2mW/10Ms/s specifications are quite aggressive.
You might want to check on the definition of the "ADC", for example,
does the ADC include the voltage reference generator? Or simply, a
SAR ADC needs to run 10x faster than the conversion rate so the
power and noise can be issues.

 There were a lot of good papers in late 70's/early 80's about SAR ADCs.
You might also want to look at the Prof. Michael Flynn's Design
Contest site at the University of Michigan,
http://www.eecs.umich.edu/~mpflynn/teaching/design_contest/fall_2002/contest_F02...

His students' write papers about their designs that cover the basics and
have bibliographies full of good references.

                                                                                   Best Regards,

                                                                                        Sheldon