Jess Chen,

I sent you an email with a detailed description including some figures explaining what I am trying to achieve. This might help clear things up a bit. Please feel free to contact me via email as well. I will post any outcome so that others can benefit from it as well.

Regards,
Sven

With respect to your last post you wrote:

"First, I assume the counter is reset after dumping it's output. If that is true, then I don't believe the combination of the VCO and counter constitute an integrator. Instead, I believe it is a quantizer."

Well, it should be integration and quantization. The VCO by itself constitutes an integrator. The counter performs the quantization over the sampling period before being reset. In essence, the counter qunatizes the input signal to the VCO.
If the input voltage to the VCO is higher, the VCO frequency will be higher, thus the counter will count more pulses, and thus the count value will be higher. Quantization.
But you make also a valid point when saying that the counter is a diff. as its output gives the rate or pulses per sampling period. This would indeed explain the stability of the system.

What would be a good way of modeling the counter with a variable transfer function to investigate limit cycles and stability issues for different signal magnitudes?

Thank you so much for this inspiring conversation Jess Chen.

Regards,
Sven

Jess,

One could indeed replace the VCO+counter by an integrator+qunatizer and then apply conventional methods to analyze limit cycles. However, the counter might have different properties that might not be observable when replacing it. So I am looking at a way to relate the input to the output. Assume we are talking about a 1-bit counter, then in order to have the same magnitude (count value) regardless of the input, we need to change the reset frequency of the counter. So with increasing pulse frequency of the input, the reset frequency needs to be increased, or equivalently the ratio of the VCO frequency to sampling/reset frequency needs to be constant. But what model could this be?

Sven

Sorry for not being clear enough, I guess I was just writing out my thoughts. Jess, you know when a quantizer is modeled in a modulator to investigate the systems stability, it is often replaced by a variable gain and phase uncertainty. So for example, when the input to the quantizer is small the quantizer gain has to be large to have the output magnitude stay constant at +/-1. When the input signal is large, the quan. gain will be small. Now, with the counter things are a bit different. If we assume a 1-bit counter then the output of the counter will be 0 or 1, Thus, the output magnitude is constant just like in the quantizer case. However, the input to the counter is a pulse train with variable frequency. Therefore, I was suggesting a model that will change the reset frequency of the counter so that no matter how high the frequency at the input is, the output will never be able to count to 2, for example.
This is the only way I can think of modeling the non-linearity of the counter, but again I don't know what sort of function could do.

In your last post you wrote:
"I am not sure I understand your question but I think you are asking how one could model the toggling behavior of the VCO/counter when its input is held constant. "
What kind of information would I be able to obtain from such a model where is input is held constant? I guess  it would display idle tones and limit cycles in the spectrum.

Regards,
Sven

Jess,

"Does your counter only have one bit or are you just trying to model the toggling of the last bit?"
I was just trying to make it more simple by assuming 1-bit only and to make it easier to compare to the 1-bit qunatizer case. It does not have to have only one bit. By changing the reset frequency you can change it accumulation and therefore the bits. (providing the counter can cope).

"On the variable sample rate, in the system (not the model), is it fixed or variable?"
The VCO being continuous, the only sampling (resetting) occurs at the counter, which is constant.

"I only mentioned a constant input to focus on the toggling behavior. My point is that I think the VCO/counter output oscillates all by itself, without any feedback, unless the VCO and sample rate are harmonically related.  But I think we agree on that." Since the counter is a differentiator there is indeed no need for a feedback signal. And yes, when the input is kept constant then the output of the counter will have a repetitive sequence.

Regards,
Sven