Hi Vivek,

if linearity is your only constraint (which is probably not the case), restricting your input signal to a smaller range should improve the results, of course at reduced SNR. Prober selection of the common mode voltage (respectively the DC level for single-ended signals) also helps.

Not sure whether this is the kind of answer you were looking for...

Paul

Vivek,

  This is a tough question, as you can see there are
different thoughts on this topic. Bootstrapping comes
from the "let's design a more complex circuit to
compensate for the non-idealities" school of thought.
Another approach is to make things as "simple as
possible to eliminate sources on non-ideality", please
see the following paper:

"A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With
85-dB SFDR at Nyquist Input," Wenhua (Will) Yang,
Member, IEEE, Dan Kelly, Member, IEEE, Iuri Mehr,
Member, IEEE, Mark T. Sayuk, Member, IEEE, and Larry  
Singer, Member, IEEE

The sample and hold is reduced to a switch and a
capacitor to minimize non-idealities. Given your
targets the simple is best approach may be an
appropriate one. The main constraint of this approach
is the common-mode rejection of the op-amp and
it should be  possible to design an op-amp with
good common-mode rejection at 1MHz.

                                               Best Regards,

                                                  Sheldon