I've seen some questions regarding how to implement a DC/DC transformer in VerilogA. Below is a netlist of a simple, poorly designed buck converter. I slapped the model together just to demonstrate the VerilogA model of the state space averaged switch, which I've also included. The model does not check for conduction mode or duty cycle saturation but it is a start. The netlist runs AC and transient analyses. The loop gain can be computed by taking the AC gain from the minus terminal of V3 to the plus terminal of V3. The phase should be interpreted as phase margin. If I can figure out how to insert an image, I'll add a schematic.
-Eugene
Code:// Generated for: spectre
// Generated on: Mar 21 12:59:12 2006
// Design library name: Eugene
// Design cell name: buck
// Design view name: schematic
simulator lang=spectre
global 0
include "/tools/dfII/samples/artist/ahdlLib/quantity.spectre"
// Library name: Eugene
// Cell name: buck
// View name: schematic
V2 (net05 net018) vsource type=pulse val0=0.0 val1=1.0 period=10 delay=1p \
rise=1n fall=1n width=1
E1 (net050 0 net019 0) vcvs gain=1/2.0
E0 (net019 0 net012 net05) vcvs gain=-1000
V0 (net21 0) vsource dc=10 type=dc
V6 (net018 0) vsource dc=3 type=dc
V3 (net046 net050) vsource mag=1 type=dc
I5 (0 net19 net015 net046) DcDcX
R0 (net13 0) resistor r=1
R3 (0 net012) resistor r=10K
R2 (net012 net17) resistor r=10K
R1 (net17 0) resistor r=10
C1 (net19 net13) capacitor c=100u
C0 (net19 0) capacitor c=10u
C3 (net019 net012) capacitor c=100n
C2 (net17 0) capacitor c=10u
L0 (net21 net19) inductor l=10u
L2 (net015 net17) inductor l=1u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25 \
tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=100u write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
ac ac start=1 stop=10M dec=20 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save L2:1
saveOptions options save=allpub
ahdl_include "/DcDcX/veriloga/veriloga.va"
Code://Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"
//DC to DC transformer.
//For a buck configuration, connect gg to ground, iin to the
//input filter, vout to the output inductor, and dr to the
//voltage representing duty ratio.
module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;
analog begin
// Note that I had to introduce an internal node, "intrn", to avoid a
// loop of rigid sources. i.e. replacing I(intrn,vout) with I(vout)
// produces a netlisting error associated with rigid loops.
I(iin,gg) <+ I(intrn,vout)*V(dr);
V(intrn,gg) <+ V(iin,gg)*V(dr);
end
endmodule