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Eugene

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Re: Behaviral modelling of dc-dc voltage converter
Reply #30 - Apr 04^th, 2006, 8:42am

Tanaka,

Are you seeing DC or transient convergence problems? Are you trying to run the exact same circuit I posted? If so, then I would say there's either a typo, a problem with the tool (relative to Spectre), or some syntax difference between the tools. If you are trying to use the switch model with a different circuit, then I would recommend the following diagnostic steps:

1. Check the sign of the feedback.
2. Remove the input filter, if its a transient problem.
3. Try different input voltages, reference voltages, and/or loads.
4. Try adding code to the switch model to ensure the applied duty cycle lies between 0 and 1, or even some tighter range. I may post such lines later.
5. You could also try ramping up all independent sources from zero, either with a transient analysis or a swept DC analysis. I am not 100% sure but I think a swept Cadence DC analysis uses the previous swept result for the next initial guess. This trick worked for me just yesterday. It lets you "sneak up" on the correct operating points. There may even by an option to ramp sources automatically without setting up an explicit sweep. I am guessing here because I've never used the Silvaco tool.

I would only touch the tolerances as a last resort. As I said in my last post, I am seeing convergence issues in a boost application of the switch. I am somewhat surprised by the problem, especially because the resistor that triggers it only needs to be 100 pico Ohms. I don't have much time to investigate it because it has nothing to do with my job. I'm looking at it just for personal interest.

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Eugene

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Re: Behaviral modelling of dc-dc voltage converter
Reply #31 - Apr 4^th, 2006, 11:12am

Here's the boost circuit I'm trying. The 10pico Ohm resistor works but 100pico Ohms causes convergence errors. Anyway, the new switch model has duty cycle clamping. The model is not yet smart enough to change conduction modes on the fly. It's possible with macro models, I have just not tried it yet with VerilogA. The basic switch model is the same. I've just reconnected it to model a boost converter instead of a buck converter.

-Eugene

Code:

// Generated for: spectre
// Generated on: Apr �4 11:03:02 2006
// Design cell name: boost
// Design view name: schematic
simulator lang=spectre
global 0
include "/tools/dfII/samples/artist/ahdlLib/quantity.spectre"

// Cell name: boost
// View name: schematic
L1 (net27 net13) inductor l=1u
C0 (net25 net052) capacitor c=20u
C2 (net25 0) capacitor c=10u
C3 (net37 net33) capacitor c=1u
R8 (net052 0) resistor r=2
R9 (net035 net27) resistor r=10p
R1 (net25 0) resistor r=10
R2 (net33 net25) resistor r=10K
R3 (0 net33) resistor r=10K
I7 (net25 0 net13 net032) DcDcX
V0 (net035 0) vsource dc=3 type=dc
V6 (net42 0) vsource dc=4.5013 type=dc
V3 (net032 net39) vsource mag=1 type=dc
E0 (net37 0 net33 net34) vcvs gain=-100
E1 (net39 0 net37 0) vcvs gain=1/2.0
V2 (net34 net42) vsource type=pulse val0=0.0 val1=100.0m period=10 \
	 �delay=1p rise=1n fall=1n width=1
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25 \
 � �tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
 � �digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
 � �sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=10m write="spectre.ic" writefinal="spectre.fc" \
 � �annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
ac ac start=.001 stop=10M dec=20 annotate=status
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts �where=rawfile
saveOptions options save=allpub
ahdl_include "/DcDcX/veriloga/veriloga.va"

Code:

//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;

real dutycycle;
analog begin
 � if (V(dr)>1) dutycycle = 1;
 � else if (V(dr)<0) dutycycle = 0;
 � else dutycycle = V(dr);
 � I(iin,gg) <+ I(intrn,vout)*dutycycle;
 � V(intrn,gg) <+ V(iin,gg)*dutycycle;
end
endmodule

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akai_densha

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Posts: 8
Tokyo

Re: Behaviral modelling of dc-dc voltage converter
Reply #32 - Apr 5^th, 2006, 6:46pm

Eugene-san,
Thank you so-much!

Actually I use same Verilog-A model provided by you.

The problem is with verilog-A transformer model ( while useing in silvaco verilog-A).
I try to simulate just the verilog-a code with iin=5V, dr=0.5V gg=0V & vout connected to the LCR network (same as the spectre netlist given by you). When I run a .op simulation, The voltage at "vout" is 0 and the current through the "vout" is zero & current drawn to terminal "iin" is zero, but voltage at "intrn" is 2.5!

So, I suspect that the voltage and current at "intrn" node is not being given out to "vout" terminal.

Please let me know your suggestions,
& also Is there a way to implement this DC transformer without the intrn node?

Thank you
Masahiro Tanaka

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Jess Chen

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Posts: 380
California Bay Area

Re: Behaviral modelling of dc-dc voltage converter
Reply #33 - Apr 5^th, 2006, 7:21pm

Masahiro-san,

Yes, there is a version without the internal node (see below). Please let me know if this helps.

-Jess

Code:

//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;

real dutycycle;
analog begin
 � if (V(dr)>1) dutycycle = 1;
 � else if (V(dr)<0) dutycycle = 0;
 � else dutycycle = V(dr);
 � I(iin,gg) <+ I(gg,vout)*dutycycle;
 � V(vout,gg) <+ V(iin,gg)*dutycycle;
end
endmodule

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« Last Edit: Apr 6^th, 2006, 12:31am by Jess Chen »

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akai_densha New Member Offline Posts: 8 Tokyo	Re: Behaviral modelling of dc-dc voltage converter Reply #34 - Apr 5^th, 2006, 8:44pm Chen-san, Thank you! This code gives me Matrix is singular problem! Tanaka
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Jess Chen Community Fellow Offline Posts: 380 California Bay Area	Re: Behaviral modelling of dc-dc voltage converter Reply #35 - Apr 6^th, 2006, 12:37am Tanaka-san, Do both switch models cause convergence problems? Does your input filter have any series resistance between the input voltage and switch? -Jess
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akai_densha New Member Offline Posts: 8 Tokyo	Re: Behaviral modelling of dc-dc voltage converter Reply #36 - Apr 6^th, 2006, 1:14am Chen-san Thank you! onry second switch model give me convegence problem. The first switch model (2006/03/21) give me no convegence problem but give me problem in "intrn" node. I have no series resistance between input voltage and switch. Tanaka
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Jess Chen

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Posts: 380
California Bay Area

Re: Behaviral modelling of dc-dc voltage converter
Reply #37 - Apr 6^th, 2006, 9:25am

Tanaka-san,

I hope I am using the "san" address correctly. Please let me know if I am not.

Does the switch work if you open the loop? i.e. try driving the dr pin with a 0.5 volt DC source. The DC output voltage should be exactly half the input voltage.

In any event, I usually try to simplify such circuits to the point where any further simplification removes the problem. Sometimes the simplification process reveals the offending element so that you can then fix the problem. At the very least, the simplification process should produce a non-proprietary testcase you can send to your simulator vendor and/or post in this Forum.

-Jess

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akai_densha

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Tokyo

Re: Behaviral modelling of dc-dc voltage converter
Reply #38 - Apr 9^th, 2006, 6:09pm

Chen-san
"san" is a common practice in Japan. You are ok!

The DC transformer dont work with .op simulation, The output is always zero. Ok , I try to fix
the problem & send to this forum.

The verilog-A in Silvaco refer to Accellera Verilog-AMS LRM version 2.2 , Sep 2004.
I begin to wonder if this is different from Cadence version of Verilog-A in IC5.1.41?

Tanaka

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Jess Chen

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Posts: 380
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Re: Behaviral modelling of dc-dc voltage converter
Reply #39 - Apr 10^th, 2006, 8:22am

Tanaka-san,

I can't help you with VerilogAMS or the Silvaco implementation. I do not have much experience with AMS and I have never used Silvaco tools. But from what I've seen in this Forum, if the problem is due to different interpretations of the language, the problem is usually syntactical and caught right away by the parser, before simulation ever starts. I'd be interested in seeing your code if you can post it. Also, someone else more familiar with AMS might be able to spot the problem.

-Jess

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akai_densha

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Re: Behaviral modelling of dc-dc voltage converter
Reply #40 - Apr 10^th, 2006, 5:42pm

Chen-san,
I dont get any simulation error. Only no result Sad

The code is same as given by you

//DC DC Transformer
`include "constants.h"
`include "discipline.h" //discipline.h in Silvaco

module DcDcX(gg, iin, vout, dr);
inout gg, iin, vout;
input dr;
electrical gg, iin, vout, dr, intrn;

analog begin

I(iin,gg) <+ I(intrn,vout)*V(dr);
V(intrn,gg) <+ V(iin,gg)*V(dr); // Nothing comes out at vout for .op. vout is connected to ground with a resistor

end

endmodule

The second code is without the intrn node.

//This code give me "Matrix is singular" error while simulation
module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;

real dutycycle;
analog begin
if (V(dr)>1) dutycycle = 1;
else if (V(dr)<0) dutycycle = 0;
else dutycycle = V(dr);
I(iin,gg) <+ I(gg,vout)*dutycycle;
V(vout,gg) <+ V(iin,gg)*dutycycle;
end
endmodule

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Jess Chen Community Fellow Offline Posts: 380 California Bay Area	Re: Behaviral modelling of dc-dc voltage converter Reply #41 - Apr 10^th, 2006, 7:42pm Tanaka-san Could you also post the simplified schematic or netlist? Perhaps I could spot something with the rest of the testbench. -Jess
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akai_densha

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Re: Behaviral modelling of dc-dc voltage converter
Reply #42 - Apr 10^th, 2006, 9:52pm

Chen-San,
This is netlist (The node "intrn" inside the verilog-A block is 2.5V but vout is zero)

* C:\Silvaco\work\test Tue Apr 11 13:35:49 2006
**
* Gateway 2.4.1.R Spice Netlist Generator
**
* Simulation timestamp: 11-Apr-2006 13:35:49.00
**
*
* Schematic name: test
*
R1 GND NET2 1k
V1 VDD GND DC 5
V2 NET1 GND DC 0.5
YVLGDCDCX1 GND VDD NET2 NET1 DCX_VLG
*
* Global Nodes Declarations
*
.GLOBAL VDD GND

*
* End of the netlist

*
* Markers to save
*
.SAVE ALL(I) ALL(V)

****************************************
*VERILOG-A
.VERILOG "dcdcx.va"
****************************************

******* ANALYSIS ******
.op
*
*
***** MODEL �*****
*
.MODEL DCX_VLG VLG MODULE = DcDcX

.END

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conv.jpg

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Eugene

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Posts: 262

Re: Behaviral modelling of dc-dc voltage converter
Reply #43 - Apr 11^th, 2006, 11:09am

Tanaka-san,

I tried your circuit with Spectre and saw the correct output voltage (2.5 Volts). The fact that with your simulator, the model with the internal node gives the correct voltage at the internal node but not at the output node tells me that your simulator is not handling current probes correctly. The model with the internal node should short the internal node to the output node. Instead, the simulator appears to leave the two nodes unconnected. Try the model below. This model should NOT work. Your simulator should complain of rigid loops, a shorted voltage source. If your simulator does not complain, then it is not handling current probes correctly but perhaps this trick works for your simulator.

You do not have to remove the duty ratio clamping from your model. You only need to add the vsource line.

-Eugene

Code:

//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;
vsource #(.dc(0)) vpb(intrn,vout);
analog begin
 � I(iin,gg) <+ I(intrn,vout)*V(dr);
 � V(intrn,gg) <+ V(iin,gg)*V(dr);
end
endmodule

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Eugene

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Posts: 262

Re: Behaviral modelling of dc-dc voltage converter
Reply #44 - Apr 11^th, 2006, 11:45am

Tanaka-san,

You could also try the model below, which should work with your simulator. The model below uses a small parameterized resistor to sense current.

-Eugene

Code:

//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;
parameter real rpb=1.0m;
resistor #(.r(rpb)) rsense(intrn,vout);
analog begin
   I(iin,gg) <+ (1.0/rpb)*V(intrn,vout)*V(dr);
   V(intrn,gg) <+ V(iin,gg)*V(dr);
end
endmodule

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