Hi all! I have some problems with verifying SOI design, including MOS transistors with five terminals (common terminal for nmos and pmos - substrate under buried oxide). Step 1 in RCX procfile includes FOX and gate oxide and I can not include substrate (metal) and buried oxide (dielectric) under this layers. Without establishing connectivity to fifth terminal it's impossible to run RCX without errors. May be someone know any tool or method for describing SOI structure and parasitic extraction SOI design?

                                                                                            Best regards