You usually get a malformed device in Assura LVS when the
extraction step can not proper extract the device terminals.
E.g. the extraction step can not build the device terminals because
they were not drawn correctly or one terminal for the device is missing.  

Either your transistor is not drawn correctly or there is a bug
in your command rule files "extract.rul" or in your setup,
run time switches probably.
Quote:

This is what always happen the extraction step, extracts every single
transistor in your layout, they were then merged later in the process,
if they were parallel, to transistors with multiple gate fingers.

As first step check for mergeParallel in the Assura docs.


Bernd