Pinhead
New Member
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Posts: 6
Germany
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Hi Guys,
is there any possibility to set a parameter with a variable ?
I need that for an instantiation of a verilog module in a module, i wanna overwrite the parameters of the instantiated module with a variable.
generate genvar x for (x=0, x< 8, x=x+1) begin: T my_osc #(var1[x]); end endgenerate
Thanks!
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