Hi everybody,
I had recently a problem that may be a via or pin extraction problem:
I get an open circuit when extracting with Assura RCX in "C only" mode but a correct extraction when using "RC" option (although I have correct LVS -and visual- check on the layout).

I use Cadence 5.033, Assura version 5.1.41 with IBM 7WL V1.4.0.4DM design kit.

Did I something wrong, does somebody have any idea about this issue ?

Thanks a lot

Jaqijak