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Charge Pump DC/DC Converter Stability! (Read 1575 times)
stephen_chou
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Charge Pump DC/DC Converter Stability!
Dec 06th, 2006, 6:51pm
 
Hi all,
I'm designing a doubler charge pump DC/DC converter, which is current mode structure(refer to Gerhard Thiele, Erich Bayer,"Current Mode Charge Pump: Topology, Modeling and Control").
I meet the stability problem in my design! The silicon has oscillation but I can't get the oscillation result from my simulation, from my transient simulation result, everything is fine! Does anybody can give me some advice about this  ?
Thanks in advance!
P.S. my simulator is spectre, and gear2 method.

Stephen
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sheldon
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Re: Charge Pump DC/DC Converter Stability!
Reply #1 - Dec 8th, 2006, 11:21pm
 
Stephen,

 Try running a periodic stability analysis and look at your gain and
phase margin. It seems to work for the this type of design. The other
thing to explore is how complete is your model does it include interconnect
parasitics, packaging parasitics, and board parasitics? Are you using an
ideal capacitor model or a does the model include ESR and ESL? ...?

                                                       Best Regards,

                                                         Sheldon
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stephen_chou
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Re: Charge Pump DC/DC Converter Stability!
Reply #2 - Dec 10th, 2006, 7:38pm
 
Thanks Sheldon for your reply!
I haven't used pstb analysis before, is it a tool of spectreRF? I haven't license for spectreRF... Sad Do you know which kind of analysis of spectre can do the same work?
Yes, I add some parasitic parameters in my simulation, but just include ESR for capacitors, and ESL for bonding wire.

Best regards,
Stephen
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sheldon
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Re: Charge Pump DC/DC Converter Stability!
Reply #3 - Dec 11th, 2006, 1:14am
 
Stephen,

  Yes, periodic stability analysis is part of SpectreRF. Unfortunately, the
Charge Pump is driven by a periodic signal and has a periodic response.
So it is well suited to be analyzed by SpectreRF's time-domain PSS analysis.
I do not believe that there is an alternative solution unless you can get
the state-average model simulations to correlate with measured results.
In that case, you could use Spectre's stability analysis to analyze the
loop's characteristics. BTW, when you analyzed the loop stability using
the model in the article by Thiele and Bayer  did you include the capacitor
parasitics in the stability analsysis?

                                                                Best Regards,

                                                                   Sheldon
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stephen_chou
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Re: Charge Pump DC/DC Converter Stability!
Reply #4 - Dec 11th, 2006, 2:05am
 
Sheldon,
The result almost same if I add 50m ohms ESR to output capacitor. I found there is also a PSS analysis method in Spectre. How do you think about this PSS analysis for charge pump analysis? I haven't use this kind of analysis before, if it possible, can you give me some tutorial material about this?

Thanks again,

Stephen
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RobG
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Re: Charge Pump DC/DC Converter Stability!
Reply #5 - Dec 11th, 2006, 3:43pm
 
Stephen,
If transient analysis isn't showing instability (i.e. ringing during start-up or a step change in load current) I wouldn't think PSS would either.  Since you are getting similar results with more series ESR, perhaps it is the bond wire inductance that is bumping up your feedback signal - especially if you didn't kelvin connect the feedback signal to the Load capacitor.  DC current loading may play a role, and it wouldn't surprise me if some large disturbance wouldn't set up a non-linear oscillation.  Other than that, with all those inversions and series resistances, I can see where unaccounted parasitics could generate secondary poles.  My first guess would be the parasitic cap at the inverting node of the amplifier, then across R1.  The loop M7/M6 looks odd to me too.  

The diodes probably have a parasitic bipolar associated with them.  It would get real exciting if your diode actually doubled the current somehow.

So.... I'm guessing you need to figure out what parasitic you are missing instead of PSS.

Sometimes you can force the output to a known voltage with a power supply and monitor current for oscillations.  If you can find regions (i.e. output levels corresonding to different load currents) where it is stable, this might help point you to the right answer.

I briefly looked at the paper you referenced.  I expect you know this, but that is a clever scheme that operates differently than your normal charge pump.  They use the "Flying capacitor" as a level shifter, not a "Flying Capacitor."  If you are using the flying capacitor in the traditional way to actually transfer the charge then the stabilizing parameters are completely different.  Still, I'd think simulations would predict what you are seeing.  

Hope this helps at least a little,
Rob
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stephen_chou
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Re: Charge Pump DC/DC Converter Stability!
Reply #6 - Dec 11th, 2006, 7:11pm
 
Hi Rob, I think that maybe your analysis make sence!
But there is still something I don't understand. I resolved the oscillation by FIB, but the transient simulation result between before-FIB and after-FIB is almost same. If the reason is because of parasitic parameters(i.e. ESR,ESL,bongding wire inductance ...), how can I explain this?
Sheldon and  Rob, sorry for my unclearly description. I just used the current mode theory that describe in the paper which I refered. The current mode method just make sure the output impedance of chargepump higher enough compared to load impedance. Therefore the output pole is almost only depend on load current and output capacitor.
There is some difference between my structure and this paper's. For example, there are no R1, M6/M7 loop, diode D1 and D2.
Rob,
I don't understand what you said "If you are using the flying capacitor in the traditional way to actually transfer the charge then the stabilizing parameters are completely different." You know, the tranditional doubler chargepump converter is using 4 switchs and a flying capacitor. So what's the difference do you mean?
Thanks,
Regards,
Stephen
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RobG
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Re: Charge Pump DC/DC Converter Stability!
Reply #7 - Dec 12th, 2006, 7:43am
 
That's great that the FIB worked.  It is hard to guess what parasitic was responsible without having more detail about the circuit and what you fibbed out.

I've only skimmed the paper so I may have missed something, but my "traditional way" would correspond to their "voltage mode."  In the "traditional" mode you are using the flying capacitor to transfer the charge.  for example, during "charge phase" you put on a controlled amount of charge, and during the "discharge phase" you discharge the flying capacitor by putting it in parallel with the load capacitor.  When you do that, the size of the capacitor as well as the charging time figure into the stability criteria.  The implication of Fig. 2 is that using a current source changes the stability criteria... this isn't necessarily true because you can use a current source to charge the capacitor during the "charge phase."  

I like the idea presented in the paper... but at first glance it looks more like a linear regulator with a series capacitor used for level shifting so that the feedback amplifier can operate beyond the rails.  Therefore, stability analysis should be similar to that of an LDO.

I hope you'll let us know what it was that was causing the instability.
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Re: Charge Pump DC/DC Converter Stability!
Reply #8 - Dec 13th, 2006, 10:46pm
 
Sorry for replying so late! Please let me introduce my debugging process:
The reason of instability is because of not enough phase margin in my design itself (of course it is! Smiley ). I tried my guess by FIB and it worked. This work of FIB will changed the loop's phase margin, but I'm not pretty sure how it affect the phase margin. So I did some mathematic analysis and get some result. You know, I can't verify my calculation by FIB, I can only verify it by simulation. So...that's why I asked this question about the topic.
I can't get the same result from simulation compared with test.
I runed 2 simulation, one is the original schematic with parasitic parameters(ESR and ESL). The other is the modified schematic based on FIB and with the same parasitic parameters(ESR and ESL). Unfortunately, I get the same result, they are both stable. Sad
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