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yagi

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Layout techniques for matching LOD effects
Dec 31^st, 2006, 10:23pm

Hello everyone,
I am using TSMC 90nm and having dc bias problems in the post-layout simulations due to LOD effect (SA and SB parameters).

1. For a perfect current mirroring, is it required to match (SA+SB) or SA and SB of matching transistors?
2. Are there any good references on techniques to use during the layout to get area efficient analog layouts.

Please suggest me.

Yagi

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emad

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Cairo, Egypt

Re: Layout techniques for matching LOD effects
Reply #1 - Jan 1^st, 2007, 12:12am

Hello Yagi,

we've seen the same issue in TSMC 130nm and 90nm. What we did is that we matched these parameters too to get better mirroring. The chip is still in verification phase so I can't confirm any success but at least they are matched in post-layout simulations.

As for a good book, the best I know of is that Alan Hasting, the art of analog Layout.

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uncle_ezra Community Member Offline Posts: 90	Re: Layout techniques for matching LOD effects Reply #2 - Jan 1^st, 2007, 4:53pm Add dummy transistors or at least a dummy poly to reduce LOD effect
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yagi New Member Offline Posts: 6	Re: Layout techniques for matching LOD effects Reply #3 - Jan 1^st, 2007, 7:17pm Hello Emad, 1. Did you match (SA+SB)s or SAs and SBs of transistors? 2. What kind of matching techniques did you use. Hastings book does not show anything on this topic. can you help. Ezra, 1. How do dummies help in matching LOD paramaters(SA and SB). Thanks, Yagi
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uncle_ezra

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Re: Layout techniques for matching LOD effects
Reply #4 - Jan 1^st, 2007, 9:12pm

First of all I believe TSMC model includes LOD effect, so this effect is included in the simulation.

From what I know (not a device expert) LOD effect increseases with larger device width. So you should first avoid using large devices. If you use minimum SA/SB significant LOD effect occurs. One way to ameliorate is to add a dummy poly at the edges to ensure uniform and stable poly CD. A better solution is to add a dummy transistor at both edges.

Also you will probably have hard time finding references on LOD effect since this effect only started to become significant recently. We see some of this effect in 0.13um and its even more pronounced in 90nm and 65nm and so on. So foundries have started to include LOD effect model in simulation to reflect this problem.

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bernd Senior Member Offline Posts: 229 Munich/Germany	Re: Layout techniques for matching LOD effects Reply #5 - Jan 2^nd, 2007, 12:37am Dear Yagi, have a look at my presentation at CDN Live EMEA 2006. "An Assura geometry extraction and Spectre re-simulation flow to simulate Shallow Trench Isolation (STI) stress effects in analogue circuits". There are some layout techniques included at the end. Bernd
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yagi

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Re: Layout techniques for matching LOD effects
Reply #6 - Jan 2^nd, 2007, 7:36pm

Hello Brend,
The presentation slides you have made is really very useful. But I could not understand following things in your slides:
1. On slide 20, the numbers below the layout what do they indicate? Are they the SA or SB, if so then why are those number(25.19) for middle N2 transistor getting reduced with addition of dummies, I see an increase in distance from poly to OD edge(SA or SB). I will be grateful if you can explain me this aspect.
2. Can we re-use this technique to match N different transistors(wth different fingering ratios) sharing same diffusion, by adding 2 dummy transistors on each side of OD and putting guard rings. If not, what should be logic to extend this idea to match higher number of transistors.

I found this issues right before tapeout, so lot of pressure on me to fix it. These suggestions are of great help to me.

Regards,
RK

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bernd

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Munich/Germany

Re: Layout techniques for matching LOD effects
Reply #7 - Jan 3^rd, 2007, 7:09am

Dear Yagi,

Quote:

1. On slide 20, the numbers below the layout what do they indicate? Are they the SA or SB, if so then why are those number(25.19) for middle N2 transistor getting reduced with addition of dummies, I see an increase in distance from poly to OD edge(SA or SB). I will be grateful if you can explain me this aspect.

The numbers below the layout indicating the drain current of the single MOS finger. The numbers on the right side are the sum of the drain current for the reference respectively the output transistor, compare with slide 19.
The drain current values were got form the re-simulated layout, with the previous described flow.

Quote:

2. Can we re-use this technique to match N different transistors(wth different fingering ratios) sharing same diffusion, by adding 2 dummy transistors on each side of OD and putting guard rings. If not, what should be logic to extend this idea to match higher number of transistors.

I'm not realy clear on how your layout does look like "N different transistors (wth different fingering ratios) sharing same diffusion", but in general this is the layout technique to reduce STI stress effects, just explained on a handy
example. I have not seen any other technique so far in the publications I looked at (not all are referenced).

Bernd

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