Dear Yagi,
Quote:1. On slide 20, the numbers below the layout what do they indicate? Are they the SA or SB, if so then why are those number(25.19) for middle N2 transistor getting reduced with addition of dummies, I see an increase in distance from poly to OD edge(SA or SB). I will be grateful if you can explain me this aspect.
The numbers below the layout indicating the drain current of the single MOS finger. The numbers on the right side are the sum of the drain current for the reference respectively the output transistor, compare with slide 19.
The drain current values were got form the re-simulated layout, with the previous described flow.
Quote:2. Can we re-use this technique to match N different transistors(wth different fingering ratios) sharing same diffusion, by adding 2 dummy transistors on each side of OD and putting guard rings. If not, what should be logic to extend this idea to match higher number of transistors.
I'm not realy clear on how your layout does look like "N different transistors (wth different fingering ratios) sharing same diffusion", but in general this is the layout technique to reduce STI stress effects, just explained on a handy
example. I have not seen any other technique so far in the publications I looked at (not all are referenced).
Bernd