Hi all!

This topic is related to http://www.designers-guide.org/Forum/YaBB.pl?num=1167842389/0.

When I tried to simulate the model posted within the previous topic, I achieved an error from AMS Designer's solvability check (see error message below). Nevertheless, I am pretty sure, that the DAE system is solvable. The simulator is probably confused by the "abnormal" formulation of the following equation:

 (VD, ID, CJ) == proceqs(VIN, IIN, VOUT, IOUT, VD, ID, CJ, dIDdt, dVDdt) TOLERANCE "Current";

Is there a way to disable the solvability check?

Thanks for your help!
Daniel

-------------------------------------- BEGIN ERROR MESSAGE --------------------------------------------
ncvhdl diode_fulleq_seq.vhd
ncvhdl: 05.83-b001 Engineering Build Dated Fri Sep  8 18:12:42 2006 Generated on amsfarmlnx14.cadence.com: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ARCHITECTURE dae OF mydiode IS
              |
ncvhdl_p: *E,SCSUMM (diode_fulleq_seq.vhd,24|15): Solvability: Summation Check failed. 5 simultaneous statements found; 7 are required in this architecture.
-------------------------------------- END ERROR MESSAGE --------------------------------------------

I agree on the background of the solvability check.

But the equation posted above should be accounted as three equations, as it determines three variable values (see the referenced posting in VHDL-AMS group for complete model). Also there are 7 variables and only 5 simultaneous statements, solvability should be guaranteed.

The full model is posted in this thread:
http://www.designers-guide.org/Forum/YaBB.pl?num=1167842389/0#0

I also noted there that the formulation (computing CJ instead of QJ) is not charge-conserving, though that's a separate question.