hi, I m looking for a good code of a clocked comparator (it s a part of designing first order delta-sigma modolator),wenn I simulate the comparator alone, is working fine,but wenn I implemented in the whole circuit I donīt get the result what i expected,I donīt know if my code is a good one.I use cadence and verilog A to implement my circuit .here is the code what I use:
// VerilogA for senna,comparateur, veriloga
`include "constants.vams"
`include "disciplines.vams"
module comparateur(inp, inn, Clk, vp,vn);
input inp, inn;
voltage inp, inn;
input Clk;
voltage Clk;
output vp,vn;
voltage vp,vn;
parameter real vth = 0.6;
parameter real dir = +1 from [-1:1] exclude 0;
branch(inp,inn) in;
real hold;
analog begin
@(cross((V(Clk)-vth), +1)) begin
if (V(in) > vth)
hold = 1.2;
else
hold = -1.2;
end
V(vp) <+ hold;
V(vn) <+ -hold;
end
endmodule
can somebody help me und give me a good code or recommendations?
best regard
senyou