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clocked comparator in verilog A (Read 14209 times)
senyou78
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germany
clocked comparator in verilog A
May 14th, 2007, 6:12am
 
hi, I m looking for a good code of a clocked comparator (it s a part of designing first order delta-sigma modolator),wenn I simulate  the comparator alone, is working fine,but wenn I implemented in the whole circuit I donīt  get the result  what i expected,I donīt know if my code is a good one.I use cadence and verilog A to implement my circuit .here is the code what I use:
// VerilogA for senna,comparateur, veriloga

`include "constants.vams"
`include "disciplines.vams"

module comparateur(inp, inn, Clk, vp,vn);
input inp, inn;
voltage inp, inn;

input Clk;
voltage Clk;

output vp,vn;
voltage vp,vn;

parameter real vth = 0.6;
parameter real dir = +1  from [-1:1] exclude 0;
branch(inp,inn) in;
real hold;

analog begin
     @(cross((V(Clk)-vth), +1)) begin
           if (V(in) > vth)
                 hold = 1.2;
           else
                 hold = -1.2;
     end
     V(vp) <+ hold;
       V(vn) <+ -hold;
end
endmodule
can somebody help me und give me a good code or recommendations? Sad
best regard
senyou




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Eugene
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Re: clocked comparator in verilog A
Reply #1 - May 14th, 2007, 8:00am
 
Off hand I don't see any problem with your code. However, when I run into compatibility problems between behavioral and device level models, it is usually because the behavioral model does not have the correct common mode voltage. You may want to check the common mode voltage your device level models expect against the common mode voltages your behavioral model produces. You may also want to make sure the input to your clock signal indeed crosses the threshold your behavioral model expects.
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Geoffrey_Coram
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Re: clocked comparator in verilog A
Reply #2 - May 15th, 2007, 4:03am
 
My first guess is that the "voltage" discipline is causing trouble when connecting to a real circuit; you should try "electrical" instead for all the ports.

The other thing that struck me as odd was this:

  V(vp) <+ hold;
      V(vn) <+ -hold;

I'd have expected V(vp, vn) <+ hold; to set up a voltage difference across the pins.  What you've got there defines a pair of voltages, one which sets the voltage from vp to ground and the other sets the voltage from vn to ground.  This may be releated to Eugene's comment about common-mode voltages.
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senyou78
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germany
Re: clocked comparator in verilog A
Reply #3 - May 16th, 2007, 1:43am
 
thanks  for your reply:)
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Sarah Ali El-Sayed
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Re: clocked comparator in verilog A
Reply #4 - Aug 30th, 2015, 7:06am
 
I think the model is not working because of the ideal rise and fall properties!
I need help to model a rising edge function?
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Ken Kundert
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Re: clocked comparator in verilog A
Reply #5 - Aug 31st, 2015, 8:13am
 
Replace the analog block with:
Code:
analog begin
     @(cross((V(Clk)-vth), +1))
	     hold = V(in) > vth;
     out = transition(hold, 0, tt);
     V(vp) <+ out;
     V(vn) <+ -out;
end 

where tt is a nonzero transition time and out is a real variable.

-Ken
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