feiyue
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Posts: 15
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Thank you very much,Mr. Eugune! I design a type 3 error amplifier ,it seems very classical and is described in detail in the book of "switching power supply design". I choose two pole at the same frequency and is 5 time higher than defined unit-gain bandwidth and two zero at 1/5 unit-gain bandwidth. I check it using matlab,the phase margin is 60deg. But if i delete the capacitor which is series connected to the integrating resistor R2,then regulator works ok,so i don't know what is the exact problem. is it because the error amplifer without a dc feedback? but i think for a whole regulator,the dc feedback is automatic established.Is it right? also i don't know whether there are some specific attention i need to pay for the correct simulation. I don't know how to construct a stata space averaged model.is there any reference?
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