Yes, you can intuitively assess whether or not a circuit has a pole-zero doublet.
Look for 2 parallel signal paths from input to output. When one signal path has a pole that the
other signal path does not have, a pole-zero doublet will arise.

Regards

Peter

Thanks for your valuable reply.I think in differential pair pole zero will come because of parallel path,but those are 2X distance,so does it impact any settling?Is there any other circuits which will give double(give me some examples).And more over is there any other impacts  on time response other than settling?
Thank,
Rajasekhar.

Yes, that is an excellent paper, Berti.
Check out Klas Bult's famous paper, something about a fast settling 90dB amplifier...
Basically another circuit which involves doublets if you're not careful is that of a gain-boosted amplifier. Just make sure the UGBW of the gain-boost amps is greater than the -3dB freq of the main amplifier.

I have a question and was wondering if ac simulation can find the effect of pole-zero doublet. Thanks.

I go with Rajasekhar and what he said is pretty much like what I heard about the effect of pole-zero doublet in AC simulation. Thanks again.

Hi,

Indeed, there is a very simple way to predict that there is a doublet without doing any math at all. I assume that you have not read the classic paper by Bult and Geelen ("A fast settling CMOS Opamp for SC Applications with 90 dB DC Gain" which appeared in the JSSC, Dec. '90 issue).

Look at the gain profile of a gain-boosted amplifier for the case where the -3dB bandwidth of the main amp is f0, and for the boosting amp f1, where f1 << f0 (as a simple example). Say the main amp has gain G0, the boosting amp G1, both in dB.

Now the gain at DC is G0 + G1, and stays so until f1, where it starts to drop by 20 dB/dec, until it reaches f0 upon which it becomes constant at G0 dB until you reach f0.

So, the gain first drops and then it becomes flat, hinting that a pole is followed by a zero. That's all there is to it really.

Regards,

Vivek

Hi Rajshekhar,

As far as I remember, the paper also states that the auxiliary amp's bandwidth should be higher than the overall loop bandwidth (which is also the logical conclusion you have drawn), and so I see no contradiction. Maybe you have misinterpreted something.

Regards,

Vivek