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voltage limited current source (Read 1329 times)
danmc
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voltage limited current source
Aug 17th, 2011, 6:29am
 
Sometimes it is useful to have a verilog-a or AMS model for something like a bias current generator but in those cases it is also good to provide voltage limiting.  Is there a simple way to do this in Verilog-A or Verilog-AMS?  The issue is that without voltage limiting, the current sources will simply force the current no matter what and sometimes that is really not what the rest of the circuit wants!  

In the past I have done some stuff in spectre with hanging additional controlled sources that have limiting on my output node.  

Thanks
-Dan
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boe
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Re: voltage limited current source
Reply #1 - Aug 17th, 2011, 12:39pm
 
Danmc,

you can do something like Code:
if (V(ibias, vss) > 1)
   I(ibias, vss) <+ CurrentValue;
else
   I(ibias, vss) <+ 0; 


However, for better convergence you should avoid the discontinuity of the current and use a soft transition.

B O E
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danmc
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Re: voltage limited current source
Reply #2 - Aug 17th, 2011, 1:17pm
 
you mean use something like like a tanh function instead of hard compare?
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Ken Kundert
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Re: voltage limited current source
Reply #3 - Aug 17th, 2011, 3:46pm
 
I don't recommend following BOE's suggestion. That is a recipe for convergence problems. I have seen two approaches to this problem that works well. One is to carefully model current/voltage limiting. You can use http://www.designers-guide.org/VerilogAMS/functional-blocks/regulator/regulator.... as a model. Alternately, you can model a two terminal clamp that you place in parallel with the current source. It would have infinite impedance within the compliance range of the current source, but then would look like a small resistor outside that range. It would be designed so that the IV characteristics were piecewise continuous.

-Ken
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boe
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Re: voltage limited current source
Reply #4 - Aug 18th, 2011, 3:25am
 
danmc wrote on Aug 17th, 2011, 1:17pm:
you mean use something like like a tanh function instead of hard compare?
Yes; and that seems to work quite well, too.
B O E
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danmc
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Re: voltage limited current source
Reply #5 - Aug 19th, 2011, 8:36am
 
Ken Kundert wrote on Aug 17th, 2011, 3:46pm:
I don't recommend following BOE's suggestion. That is a recipe for convergence problems. I have seen two approaches to this problem that works well. One is to carefully model current/voltage limiting. You can use http://www.designers-guide.org/VerilogAMS/functional-blocks/regulator/regulator.... as a model. Alternately, you can model a two terminal clamp that you place in parallel with the current source. It would have infinite impedance within the compliance range of the current source, but then would look like a small resistor outside that range. It would be designed so that the IV characteristics were piecewise continuous.

-Ken



Thanks Ken.  I read those 2 pages from your book (which was only about arms length away) and implemented 2 boundaries instead of 1 and it seems to work like a champ.

Thanks again.

-Dan
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