Thanks BOE,
I was already using the genvar method, but missed a couple of other things.
I managed to get it working even including the parameterized number of stages. The following code shows the working model, at least for smartspice.
Code:`include "discipline.h"
module rc_ladder(in, out, gnd) ;
inout in,out,gnd;
electrical in,out, mid,gnd;
parameter r=1k ;
parameter c=1n ;
analog begin
// stage 1
I(in,mid) <+ V(in,mid) / r;
I(mid,gnd) <+ ddt( V(mid,gnd) * c );
// stage 2
I(mid,out) <+ V(mid,out) / r;
I(out,gnd) <+ ddt( V(out,gnd) * c );
end
endmodule
// parameterized version using a for loop with genvar
module rc_ladder_forloop(in, out, gnd) ;
parameter integer steps = 2;
inout in,out,gnd;
electrical [0:steps] con;
electrical in, out, gnd;
parameter r=1k ;
parameter c=1n ;
genvar k;
analog begin
for (k=0 ; k < steps ; k = k+1 ) begin
I(con[k],con[k+1]) <+ V(con[k],con[k+1]) / r;
I(con[k+1],gnd) <+ ddt( V(con[k+1],gnd) * c );
end
V(con[0],gnd) <+ V(in,gnd);
V(out,gnd) <+ V(con[steps],gnd);
end
endmodule
and the netlist should be as follows:
Code:Test RC-ladder loops
.verilog "./test.vams"
v1 in 0 PWL(0 0 5u 10 20u 10)
** Uncomment only one of the following two lines
** First line: fixed 2 stage RC ladder
** Second line: parameterized n-stage RC ladder
*YVLG_ladder in out 0 rc_ladder
YVLG_ladder in out 0 rc_ladder_forloop steps = 2
.tran 1n 20u
.iplot v(out)