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Model Exponential rising signal in Verilog-A (Read 8778 times)

aliasnikhil

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Model Exponential rising signal in Verilog-A
Feb 17^th, 2013, 7:56pm

Hi,

I am trying to write VerilogA model for a circuit that has an exponentially rising output response (like charging of a real capacitor). For example, if the input is a voltage pulse with almost zero rise time, then the output of the circuit should rise exponentially towards the final voltage.

I need this equation:
V_out = V_previous + (V_new - V_previous)*(1 - exp(-1*time/tau))

V_previous is the starting voltage.
V_new is the voltage that the output tries to reach exponentially.
tau is the time constant.

Can anyone please help me with this regard.

Thanks.
-Nikhil

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Geoffrey_Coram

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Posts: 1998
Massachusetts, USA

Re: Model Exponential rising signal in Verilog-A
Reply #1 - Feb 21^st, 2013, 10:15am

You could implement an R and a C with Verilog-A equations.

How are you thinking to "remember" the starting voltage?

Code:

module vexpout(in, out, ref);
inout in, out, ref;
electrical in, out, ref;
electrical mid;
parameter real R = 1 from (0:inf);
parameter real C = 1p from (0:inf);

analog begin
 � �I(in,mid) <+ V(in,mid) / R;
 � �I(mid,ref) <+ C * ddt(V(mid,ref));
 � �V(out,ref) <+ V(mid,ref); // output buffer
end
endmodule

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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