The scaling factor in each integrator of a CTDSM is Fs(sampling frequency). So typically 1/RC = Fs. Now you need to have feedback coefficients for each paths. In your case since second order two paths (1/s and 1/s^2). And direct path if compensated for excess loop delay.
Now these coefficients can be added to the 1/RC or at the DAC itself. That is a choice that you have to make. Typically for the first integrator R is fixed for thermal noise spec. For other integrators you can choose a R and C such that they are not too large in layout and not too small to get affected by parasitics. Also take into consideration area.
One more thing you have to take into account is the swing at the output of each integrator. Best design practice is to scale the swing to the max swing an opamp can support so that your passives won't get too big. Use node scaling for that.
These scaling factor will also come in the RC time constant of integrator.
You can watch video lectures of Dr Shanti Pavan of IIT Madras for a detailed understanding.
http://nptel.ac.in/courses/117106034/http://www.ee.iitm.ac.in/vlsi/