nosrat
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Posts: 8
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Thanks a lot Mr. Geoffrey In the verilog –A code for the model, I have done the changes you asked:
real Ids, Qs, Qd, Qg; (* desc="Cgd" *) real Cgd; (* desc="Cgs" *) real Cgs;
And for print command in Hspice, I have used below lines: .DC Vg 0 0.5 0.001 .print dc Cgd .print dc Cgs
But after running simulation, this warning appears on ‘file.lis’: **warning** (cgdntfet.sp:35) Unrecognized output type cgs on line above; The line is ignored.
ac output variable type=s not allowed for transient or dc
So still I couldn’t print them (Cgd , Cgd).
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