• Is it possible for anyone to help me about  TFET HSPICE libraries?
I couldn’t download from https://nanohub.org/publications/12
best  regards
Nosrat

Hi Dear

But I couldn’t download it. Is it possible for you to send the file to me?
I need the TFETs library of HSPICE for analyzing analog circuits. Does the file fulfill my need in your idea?
Would you do me a favor and give me a hand on this one, too?  I will really appreciate it.

Is your country subject to export restrictions?

But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitances) given applied biases.  There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."

gold -
Do you know what I mean when I say "compact model"?

Your question is analogous to asking

Can we use BSIM4 in Cadence Virtuoso for analyzing analog circuits?

The nanoHUB publication is a compact model, that is, the set of equations for a TFET (like BSIM4 is a set of equations for bulk CMOS).  There's a set of parameters, but it's probably a set for a device the researchers were using, and may not be anything close to the TFET devices you want to use.

(I'm not up on Cadence's latest branding campaigns, I know the simulator as "Spectre" not as "Virtuoso."  But you should be able to run this model in most analog/spice-like circuit simulators.)

Sorry. Verilog A code in TFET model gives the set of equations for current and capacitance and also for dc and tran simulations. I want to find conversion gain for mixer circuit. Is it possible in spice? Can you suggest me?

Hi Geoffrey
Is your country subject to export restrictions?
about this question I must say I don't know.  
But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitance's) given applied biases.  There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."
about this I agree with you but  I would use Verilog-A lookup table model and convert it to HSPICE in order to perform power consumption analysis

If you post an HSpice netlist showing how you want to measure Cgd/Cgs for a regular MOS model (eg, BSIM4), I could show you how to adapt that to use the Verilog-A TFET model.

I don't think you'd be changing the Verilog-A, though.

So, in the Verilog-A code for the model, do you see:
Code:

real Ids, Cgs, Cgd,Qg, Qs, Qd; 

?

Delete Cgs and Cgd from that line, and add these lines:
Code:

(* desc="cgd" *) real Cgd;
(* desc="cgs" *) real Cgs;
 

Then those values should be available for printing.

Alternately, you could put an ac source on the drain and measure the imaginary gate current in an ac analysis to get Cgd, or put the ac source on the source to get Cgs.