So, in the Verilog-A code for the model, do you see: Code:
real Ids, Cgs, Cgd,Qg, Qs, Qd;
Delete Cgs and Cgd from that line, and add these lines: Code:
(* desc="cgd" *) real Cgd;
(* desc="cgs" *) real Cgs;
Then those values should be available for printing.
Alternately, you could put an ac source on the drain and measure the imaginary gate current in an ac analysis to get Cgd, or put the ac source on the source to get Cgs.