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TFETs (Read 10 times)
nosrat
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TFETs
Mar 07th, 2016, 3:48am
 
• Is it possible for anyone to help me about  TFET HSPICE libraries?
I couldn’t download from https://nanohub.org/publications/12
best  regards
Nosrat
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Geoffrey_Coram
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Re: TFETs
Reply #1 - Mar 8th, 2016, 6:56am
 
I had no trouble downloading a file from that link, even without logging in.  (However, the model itself is capacitance-based, hence non-charge-conserving, and uses $table_model rather than physical equations.)
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Re: TFETs
Reply #2 - Mar 8th, 2016, 9:42pm
 
Hi Dear

But I couldn’t download it. Is it possible for you to send the file to me?
I need the TFETs library of HSPICE for analyzing analog circuits. Does the file fulfill my need in your idea?
Would you do me a favor and give me a hand on this one, too?  I will really appreciate it.
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Re: TFETs
Reply #3 - Mar 8th, 2016, 9:48pm
 
I will send my email address by PM
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Re: TFETs
Reply #4 - Mar 9th, 2016, 1:53pm
 
Is your country subject to export restrictions?

But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitances) given applied biases.  There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."
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Re: TFETs
Reply #5 - Mar 10th, 2016, 1:17am
 
Hai,

Can we use this model file in Cadence Virtuoso for analyzing analog circuits?
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Re: TFETs
Reply #6 - Mar 10th, 2016, 9:30am
 
gold -
Do you know what I mean when I say "compact model"?

Your question is analogous to asking

Can we use BSIM4 in Cadence Virtuoso for analyzing analog circuits?

The nanoHUB publication is a compact model, that is, the set of equations for a TFET (like BSIM4 is a set of equations for bulk CMOS).  There's a set of parameters, but it's probably a set for a device the researchers were using, and may not be anything close to the TFET devices you want to use.

(I'm not up on Cadence's latest branding campaigns, I know the simulator as "Spectre" not as "Virtuoso."  But you should be able to run this model in most analog/spice-like circuit simulators.)
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Re: TFETs
Reply #7 - Mar 10th, 2016, 7:54pm
 
Hai Geoffrey,

Verilog A code in TFET model gives the set of equations for current and capacitance and also for dc and ac simulations. But when I try to use this model for pss and pac analysis, it shows some error. Is it possible to run this model file for mixer and LNA circuits in spice simulator?
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Re: TFETs
Reply #8 - Mar 10th, 2016, 8:14pm
 
Sorry. Verilog A code in TFET model gives the set of equations for current and capacitance and also for dc and tran simulations. I want to find conversion gain for mixer circuit. Is it possible in spice? Can you suggest me?
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Re: TFETs
Reply #9 - Mar 11th, 2016, 7:41am
 
Do you get a "hidden state" error?

You should post this issue as a "wish" on nanoHUB.  (I suspect the problem is that the model assigns values inside if-statements, but doesn't initialize them.  Try setting Ids, Cgd, Cgs, and direction to 0 right after "analog begin" in tfet_master.va)
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Re: TFETs
Reply #10 - Mar 12th, 2016, 4:43am
 
Hi Geoffrey
Is your country subject to export restrictions?
about this question I must say I don't know.  
But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitance's) given applied biases.  There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."
about this I agree with you but  I would use Verilog-A lookup table model and convert it to HSPICE in order to perform power consumption analysis
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Re: TFETs
Reply #11 - Jun 8th, 2016, 12:14am
 
Hi,
I want to plot/print  the characteristic   Cgd  and Cgs  vs  Vds for different Vgs by using  Verilog –A  TFET  capacitor table model  from  https://nanohub.org/publications/12  
Could you tell me how to change  Verilog –A  and do that in hspice
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Re: TFETs
Reply #12 - Jun 9th, 2016, 9:55am
 
If you post an HSpice netlist showing how you want to measure Cgd/Cgs for a regular MOS model (eg, BSIM4), I could show you how to adapt that to use the Verilog-A TFET model.

I don't think you'd be changing the Verilog-A, though.
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Re: TFETs
Reply #13 - Jun 11th, 2016, 5:25am
 
Thanks Geoffrey ...
I've attached a PDF expressing my problem. would you check it, please?
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Re: TFETs
Reply #14 - Jun 13th, 2016, 8:24am
 
So, in the Verilog-A code for the model, do you see:
Code:
real Ids, Cgs, Cgd,Qg, Qs, Qd; 


?

Delete Cgs and Cgd from that line, and add these lines:
Code:
(* desc="cgd" *) real Cgd;
(* desc="cgs" *) real Cgs;
 



Then those values should be available for printing.

Alternately, you could put an ac source on the drain and measure the imaginary gate current in an ac analysis to get Cgd, or put the ac source on the source to get Cgs.
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