dog1
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Hello,
I am reading the paper from Kim and Pual Gray PLL/DLL system noise analysis for low jitter clock synthesizer design. Here I encounter the concept accumulated jitter for the first time. It says that by accumulating jitter in different cycles of PLL, it can be amplified, compared with the jitter from the VCO. This is bugs me. Because using the normal s domain analysis of PLL, we know that the phase noise of the PLL is high pass filtered. This means that the energy of phase noise/ rms jitter should be smaller compared with that of VCO. However, this paper indicates otherwise. Can anyone comment on that?
Additionally, does anyone know if the accumulated noise is taken into account of in jitter simulation using spectre?
Thanks
CHEN
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