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how to include a module in another module? (Read 1903 times)
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how to include a module in another module?
Aug 09th, 2018, 10:10am
 Hi all

 I wrote the following code (comparator.v and test_module.v), test_module is fairly simple. It just try to include comparator.v.

 However, when I try to compile the test_module.v, it reports the following errors. Can anyone help on the issue? Basically I am trying to include sub module using command "include", but I seems to have trouble on it.

 Thank you very much.

 ncverilog(64): 15.20-s022: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
file: test_module.v
module comparator(stag,ptag,tag_equal);
ncvlog: *E,EXPENM (comparator.v,1|5): expecting the keyword 'endmodule' [12.1(IEEE)].
(`include file: comparator.v line 1, file: test_module.v line 2)
       module worklib.test_module:v
               errors: 1, warnings: 0
endmodule // test_module
ncvlog: *E,EXPMPA (test_module.v,3|8): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
       Total errors/warnings found outside modules and primitives:
               errors: 1, warnings: 0
ncverilog: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).


module test_module();
`include "comparator.v"
endmodule // test_module


module comparator(stag,ptag,tag_equal);
  parameter n=16;
  input [n-1:0] stag,ptag;
  output        tag_equal;

  reg           tag_equal;
  integer       i;

//   initial begin
//   tag_equal<=1'b1;
//   end
  always @(stag or ptag)

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Andrew Beckett
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Re: how to include a module in another module?
Reply #1 - Aug 10th, 2018, 4:50am
You cannot nest modules in the Verilog standard. The SystemVerilog standard does allow nesting of modules, but the Cadence simulators do not currently support this.

However, I rather doubt you need it. I'm not sure what benefit embedding the comparator within test_module brings  you, since the comparator is not instantiated within test_module. Even if it was instantiated, there's no need to include one file in the other - you can just pass all the files to the simulator and it will compile them all, and elaboration will take care of linking them all together.


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