hi, everyone!

I want to make a CIC filter for sdadc based on verilog ams, I realized this model in simulink, and got the right simulation result, but in verilog ams, this model can not work, because the signal in this model will exceeds the limit of simulator.

**Code:**Output and IC/nodeset summary:
save 3 (current)
save 28 (voltage)
tran: time = 911.8 ns (91.2 m%), step = 5 ps (500 n%)
tran: time = 1.829 us (183 m%), step = 5 ps (500 n%)
tran: time = 2.747 us (275 m%), step = 5 ps (500 n%)
tran: time = 3.592 us (359 m%), step = 5 ps (500 n%)
tran: time = 4.443 us (444 m%), step = 5 ps (500 n%)
tran: time = 5.294 us (529 m%), step = 5 ps (500 n%)
Error found by spectre at time = 5.45705 us during transient analysis `tran'.
ERROR (SPECTRE-16384): Signal V(I5.net026) = 1.00084 GV exceeds the blowup limit for the quantity `V' which is (1 GV). It is likely that the circuit is unstable. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.

the model is as follow:

input from sdm is +1 and -1 in matlab，so in this verilog ams model，I also using +1 and -1， the reason for this， i think, maybe,the 2’s complement for real digital cic filter' operation.

the code for z-delay:

**Code:**`include "constants.vams"
`include "disciplines.vams"
module Z_INV_DIG(in, out,clk);
input in, clk;
output out;
electrical in, out, clk;
parameter real Vtrans=0.9;
parameter real tr=10p; //rise,fall time
parameter real tt=0.1p; //time tolerance
parameter real td=10p; //delay time
parameter real init_outval=0; //initial output value
integer outval;
analog begin
@(initial_step) begin
outval=init_outval;
end
@ (cross(V(clk)-Vtrans, +1, tt)) outval=V(in);
V(out) <+ transition(outval,td,tr,tr,tt);
end
endmodule

the code for divider:

**Code:**// VerilogA for forWorkShop, Divider, veriloga
`include "constants.vams"
`include "disciplines.vams"
module DIV_VA(in, out);
input in;
output out;
electrical in, out;
parameter integer ratio=8;
parameter real VHigh=1.8;
parameter real VLow=0.0;
parameter real Vth=(1.8+0.0)/2;
parameter integer dir=1 from [-1:1] exclude 0;
parameter real td=1p;
parameter real tr=10p;
parameter real ttol=1p;
integer count;
integer state;
analog begin
// @(initial_step) begin
// count=0;
// state=1;
// end
@(cross(V(in)-Vth,dir,ttol)) begin
count=count+1;
if (count==ratio) count=0;
state=(2*count<=ratio);
end
V(out) <+ transition(state?VHigh:VLow,td,tr,tr);
end
endmodule

please help,thanks very much!