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Dec 6th, 2019, 12:26am
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How to speed up RJ sim for DLL including Regulator (Read 67 times)
aks
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How to speed up RJ sim for DLL including Regulator
Nov 22nd, 2019, 5:55am
 
Hi
I am doing RJ sims for a DLL using PSS/Pnoise analysis. I want to include Regulator in my sims to assess impact of regulator noise (random) on DLL's RJ. But the sims are quiet slow. Any suggestions, how to fasten the simulations in this scenario.

Thanks
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kumar.g
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Re: How to speed up RJ sim for DLL including Regulator
Reply #1 - Dec 3rd, 2019, 5:07am
 
You can first simulate just the regulator and extract the noise of the regulated voltage for a time of say 1/low_freq_of_interest. Then use this noise in DC source of the DLL test bench as a piece-wise-linear model.
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aks
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Re: How to speed up RJ sim for DLL including Regulator
Reply #2 - Dec 4th, 2019, 4:18am
 
Thanks Kumar.. You mean noise at "low_freq_of_interest"  or spot noise at say 1MHz?
Actually I was thinking of using integrated noise over range of freq. of interest which covers (Lowest freq of interest to freqDLL/2) and use it as you mentioned.
But then the DLL must be simulated for long enough time to cover impact of the slow moving noise (pwl) spanning over lowest freq of interest (i.e lowest freq 1M Hz => 1usec!! ) which becomes very lengthy simulation and time consuming.

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kumar.g
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Re: How to speed up RJ sim for DLL including Regulator
Reply #3 - Dec 4th, 2019, 11:33pm
 
low_fre_of_interest is the lower limit of the PLL noise integration. Like you have mentioned in your post, to include the low frequency noise, you will have to simulate upto 1us. However simulating just the regulator as a standalone should speed up your simulation compared to simulating with the PLL.
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