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1 | Simulators / RF Simulators / Re: How to extract s2p files for sp probe in ADS? on: Jul 5th, 2024, 10:48am |
Started by Yashas | Post by Ken Kundert | |
Can you be more specific as to what you want? Extract from what? |
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2 | Simulators / RF Simulators / How to extract s2p files for sp probe in ADS? on: Jul 5th, 2024, 12:06am |
Started by Yashas | Post by Yashas | |
Howdy all, I am currently working on a couple of designs on ADS and am trying to extract the s2p file for the SP_probes placed around the design. All recommendations are welcome. Thanks. |
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3 | Design / RF Design / Moved: How to extract s2p files for sp probe in ADS? on: Jul 5th, 2024, 12:06am |
Started by Yashas | Post by Yashas | |
This Topic has been moved to RF Simulators by Ken Kundert. |
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4 | Modeling / Semiconductor Devices / Re: Why use macros to define Verliog-A model/instance parameters? on: Jun 27th, 2024, 8:48pm |
Started by TomH_vams | Post by Ken Kundert | |
I don't know, but if I were to guess, it is due to limitations in the various simulators they are supporting. By using defines, they can keep their standard definition of the model constant for all simulators, with the adaptation of the model to particular simulators using simulator specific defines. |
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5 | Modeling / Semiconductor Devices / Why use macros to define Verliog-A model/instance parameters? on: Jun 26th, 2024, 2:08pm |
Started by TomH_vams | Post by TomH_vams | |
Some verilog-a compact models heavily use macros to define model & instance parameters. What is the purpose and benefit of this, compared to just using conventional parameter declarations? Some examples from ASMHEMT 101.4, which defines nearly 40 such macros: `define MPRnb(nam,def,uni, des) (*units=uni, desc=des*) parameter real nam=def; `define MPRex(nam,def,uni,exc, des) (*units=uni, desc=des*) parameter real nam=def exclude exc; `define MPRcc(nam,def,uni,lwr,upr,des) (*units=uni, desc=des*) parameter real nam=def from[lwr:upr]; `define MPRoo(nam,def,uni,lwr,upr,des) (*units=uni, desc=des*) parameter real nam=def from(lwr:upr); `define MPRco(nam,def,uni,lwr,upr,des) (*units=uni, desc=des*) parameter real nam=def from[lwr:upr); `define MPRoc(nam,def,uni,lwr,upr,des) (*units=uni, desc=des*) parameter real nam=def from(lwr:upr]; `define MPRcz(nam,def,uni, des) (*units=uni, desc=des*) parameter real nam=def from[ 0:inf); `define MPRoz(nam,def,uni, des) (*units=uni, desc=des*) parameter real nam=def from( 0:inf); etc and a few specific uses in ASMHEMT: `MPRco( tnom ,27.0 ,"deg C" ,-`P_CELSIUS0,inf ," Nominal Temperature in degree Celsius" ) `MPRcc( voff ,-2.0 ,"V" ,-100.0 ,5 ," Cut-off voltage" ) `MPRoo( kt1 ,0.0e-3 ,"" ,-inf ,inf ," Temperature Dependence for Voff" ) etc I asked one of the original asmhemt developers about this, and he replied "the EDA publisher(s) wanted it". I've seen same method used in PSP, MSIMCMG, and other compact models, so it's not simply a developer's preference. What is advantage vs using simple parameter declarations? Is it a convention that I'm simply unaware of? Where would I find the relevant style manual? (I'm not a CMC member) |
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6 | Analog Verification / Analog Functional Verification / Re: Timer function can't take period input as a parameter on: Jun 11th, 2024, 5:34am |
Started by Lala878 | Post by Lala878 | |
Hey, I am sorry for the confusion, but while writing this post I realized my own mistake in calculating the period and setting up the transient simulation. I made a mistake with the analysis tran time. It is working as it should, it is making 1000 points in 6.67us (MICRO seconds) and I was simulating in 6.67ns, so of course no results to show there... and I counted the zeros wrongly... Anyway, I searched for a way to delete my post and haven't found it yet, but if pointed I can delete it. |
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7 | Analog Verification / Analog Functional Verification / Timer function can't take period input as a parameter on: Jun 11th, 2024, 5:22am |
Started by Lala878 | Post by Lala878 | |
I am making a simple decimal to binary code to shape a multibit output in verilogA. I want to use a @timer function but I noticed I can't put a parameter or variable for the period interval. Example: Code: parameter real inputFrequency = 150K; parameter integer ptsPerPeriod = 1000; real timerPeriod = (1/inputFrequency)/ptsPerPeriod; analog begin ... @(timer(0, timerPeriod)) begin ... end //timer end //analog The timerPeriod in this example is calculated correctly, I checked wih the $display() function, it is 0.00000000000667 . Simulating (in Cadence Virtuoso) in transient analysis for 1ns, the timer is never triggered. However, if I put "6.67p" for the timer period interval it works fine. Am I getting the formatting wrong? Does anybody have an advice how to make the period interval into a variable? |
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8 | Design / RF Design / Re: VCO Phase noise Discrepancy in pnoise and transient noise on: Jun 3rd, 2024, 1:16pm |
Started by Hassan | Post by Hassan | |
Hello Shawn, Thanks for your answer. I am still looking for an answer to this question. As far as I know, when I have white noise, the integral of it will have a spectrum with a slope of -20dBc/dec since its spectrum is simply multiplied by 1/s^2. I verified this using transient noise simulation, showing a -20dBc/dec slope. Please take a look at image below from "Phase Noise and Jitter in CMOS Ring Oscillators" paper. |
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9 | Design / RF Design / Re: VCO Phase noise Discrepancy in pnoise and transient noise on: May 27th, 2024, 6:17pm |
Started by Hassan | Post by smlogan | |
Dear Hassan, In case you have not determined the root cause of your observed -40 dB/decade phase noise characteristic, I believe the issue is you are applying frequency noise - not phase noise - by including the noisy 1K resistor in series with the control voltage input. In essence, the control voltage input modulates frequency. Hence, the slope of a flat noise source applied to the control voltage of the VCO will result in -40 dB/decade phase noise slope - not -20 dB/decade. Shawn |
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10 | Design / Analog Design / matching: why are small unit caps are better that a single big one in modern pro on: May 26th, 2024, 11:34am |
Started by RobG | Post by RobG | |
Pelgrom's law that matching is proportional to 1/sqrt(area) no longer seems to apply, at least with MOM finger (fringe) capacitors. I have noticed in two different processes (65nm and 22nm) that, for example, a 1000fF cap made of 100 10fF caps matches much better than a single 1000fF capacitor. In fact, the standard deviation was 12x better when 10fF unit caps were used. That's huge. This oddity is confirmed in the design manual's data, but they don't provide an explanation. Does anyone know what's going on here? It completely violates Pelgrom's findings. |
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