Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
how to design 15/16 prescaler and P, S-counter?	RF-Turbo	0	1594	Mar 5^th, 2010, 2:59am By: RF-Turbo
Sink Current Issue in OPamp	analog_chip	0	1160	Mar 4^th, 2010, 8:05am By: analog_chip
Simple math question...	Turin	3	2718	Mar 2^nd, 2010, 5:42pm By: sos
npoly vs ppoly resistor	supermoment	6	4381	Feb 28^th, 2010, 8:35pm By: supermoment
DC-OP point of Voltage Regulator	bharat	3	2728	Feb 28^th, 2010, 10:49am By: bharat
Basics for a Digital engineer to design analog Ckt	kumar.g	4	3142	Feb 28^th, 2010, 7:24am By: kumar.g
Parasitic & Floating Capacitance	Asmodeus	2	2837	Feb 24^th, 2010, 9:09pm By: ywguo
Why while testing an AMPLIFIER (test chip) in feedback configuration both R-C fe « Pages 1 2 »	Manas	24	15644	Feb 22^nd, 2010, 2:44am By: pancho_hideboo
Moved: what is vdd!* - Started by: gabc This Topic has been moved to Entry Tools by Ken Kundert
Question about Fig. 17 of the paper "Device noise simulation of DS Modulators"	alireza	2	3483	Feb 19^th, 2010, 8:55am By: alireza
design example for gm/Id methodology « Pages 1 2 »	ipyd	17	3311	Feb 19^th, 2010, 3:58am By: ywguo
pole zero doublet « Pages 1 2 »	raja.cedt	18	3974	Feb 18^th, 2010, 11:33pm By: Berti
need help choosing op-amp config « Pages 1 2 »	carporsche	19	3486	Feb 17^th, 2010, 1:32pm By: carporsche
Capacitance matching/weighting in precision analog circuits?	Maks	8	7624	Feb 17^th, 2010, 1:00am By: Maks
pole zero doublet in regulator	raja.cedt	11	575	Feb 10^th, 2010, 6:32pm By: HdrChopper
Moscap	GaAs_si	4	244	Feb 10^th, 2010, 8:11am By: GaAs_si
Class-AB rail-to-rail output stages for fully-differential op-amps	Carl F	3	187	Feb 7^th, 2010, 3:53am By: Carl F
NF and Device WIDTH	A Kumar R	0	1301	Feb 4^th, 2010, 5:42am By: A Kumar R
Gate shot noise in deep submicron technology	roland	0	1299	Feb 3^rd, 2010, 7:53pm By: roland
poly orientation in lay-out « Pages 1 2 »	Dipankar	16	2960	Feb 2^nd, 2010, 7:04am By: Berti

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