Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
a question about fluidic sys. in Verilog-AMS	lily	3	5559	Dec 18^th, 2003, 8:02am By: Ken Kundert
SpectreRF	Guneet Singh	1	3900	Nov 3^rd, 2003, 10:18am By: Ken Kundert
Design CPU16 bits, and run assembly program on it	Dang Vu Linh (Guest)	0	2786	Oct 29^th, 2003, 9:10pm By: Dang Vu Linh (Guest)
Testbench for phase domain pll	Yiming Xie (Guest)	0	3858	Sep 30^th, 2003, 9:37am By: Yiming Xie (Guest)
help on DFF modeling with set and clear	CDR	6	291	Jul 17^th, 2003, 9:54am By: Ken Kundert
Indep Source models	Geoffrey_Coram	3	162	Jul 17^th, 2003, 8:49am By: Ken Kundert
Export between VHDL-A �and Verilog-A models	SVT	0	70	Jul 14^th, 2003, 6:55am By: SVT
help on the CADENCE ahdl lib	Aigneryu	4	207	Jul 12^th, 2003, 6:34am By: Aigneryu
How to Implement Time Dependent Noise	jjrael	5	7978	Jul 8^th, 2003, 4:28pm By: pancho_hideboo
Information about JitterSim	saurabh (Guest)	1	3807	Apr 8^th, 2003, 3:07pm By: Ken Kundert

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