Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
BW of ideal comparator	Irvin73	1	3064	Nov 17^th, 2010, 8:04am By: Marq Kole
global nodes in verilog-ams	Luke Whitaker	1	2834	Nov 17^th, 2010, 7:01am By: Marq Kole
ius820+Unable to load SST2 communication library	mustangyhz	2	3917	Nov 15^th, 2010, 5:20pm By: mustangyhz
How to append data to a file instead of overwrite it in VerilogA?	wandola	1	2693	Nov 15^th, 2010, 6:23am By: Geoffrey_Coram
How to trace analog value as real value ?	sand_dolphin2	9	2029	Nov 12^th, 2010, 12:02am By: sand_dolphin2
matrix vector multiplication	Richardsim	0	1677	Oct 22^nd, 2010, 9:46am By: Richardsim
288 bit SIPO register	Prashant Babu	1	1991	Oct 20^th, 2010, 6:40am By: Prashant Babu
for checking I/O behavior	sand_dolphin2	1	1653	Oct 7^th, 2010, 1:13am By: sand_dolphin2
Printing loop variable	Peter_R_Kroon	3	2511	Oct 5^th, 2010, 4:53am By: Peter_R_Kroon
Controlling Verilog-A Module Parameters Externally	omar	3	2860	Oct 1^st, 2010, 12:24pm By: omar
Command Execution Sequence in VerilogA	neoflash	3	4490	Sep 30^th, 2010, 3:16pm By: Ken Kundert
Time as variable of array.	Streamcx	1	2091	Sep 30^th, 2010, 11:30am By: Ari
problem in compling verilog.vams code in cadence	Amit_Analog	4	777	Sep 30^th, 2010, 8:17am By: Amit_Analog
how to flush out the buffer in verilog A?	Irvin73	3	4281	Sep 29^th, 2010, 8:45am By: Geoffrey_Coram
Tristate output of Analog value	sand_dolphin2	2	2840	Sep 27^th, 2010, 1:54am By: sand_dolphin2
Transient simulation of Verilog-A model - Explanation required	kumar.g	3	2794	Sep 24^th, 2010, 1:49pm By: Geoffrey_Coram
Output of Kv when my rail-rail is 15v	kumar.g	6	193	Sep 24^th, 2010, 1:47pm By: Geoffrey_Coram
maximum integer in verilog-A/AMS	Aigneryu	5	1171	Sep 18^th, 2010, 11:22pm By: neoflash
VerilogA code for 8b/10b, 64b/66b, 128b/130b encoder/decoders	neoflash	1	3360	Sep 18^th, 2010, 2:32pm By: neoflash
Is there a identifier or something like that to access the frequency in .ac ?	mowiehowie	3	2666	Sep 9^th, 2010, 10:54am By: mowiehowie

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