Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Specifying verilog library	rajdeep	0	1115	May 31^st, 2007, 11:46am By: rajdeep
How to instantiate spectre modules in VerilogA ?	rajdeep	2	3014	May 31^st, 2007, 11:13am By: rajdeep
join strings	Croaker	4	4158	May 31^st, 2007, 3:47am By: Geoffrey_Coram
string variables in VerilogA	makelo	3	10426	May 31^st, 2007, 3:44am By: Geoffrey_Coram
terminal of instance not found on master	Croaker	4	4539	May 30^th, 2007, 9:36am By: chetan
Hierarchy Parameter Passing - Multi Level	loose-electron	3	4351	May 30^th, 2007, 9:22am By: chetan
How to make accumulator module use verilog-A?	icsoul	2	3718	May 25^th, 2007, 2:38am By: icsoul
wrapping long instantiation lines	makelo	2	2407	May 23^rd, 2007, 7:22am By: makelo
Binary counter in VerilogA	Vabzter	2	56	May 22^nd, 2007, 6:55am By: makelo
questions about the cadence pll library	calven	2	2596	May 16^th, 2007, 11:03am By: Jess Chen
cascode current source	Croaker	9	6377	May 10^th, 2007, 4:50am By: Croaker
FM VerilogA and limited noise performance	trond	7	6655	May 10^th, 2007, 12:08am By: Ken Kundert
current source convergence issues when open	Croaker	2	2658	May 7^th, 2007, 5:03am By: Croaker
decimation filter CIC, two's complement	trond	3	4214	May 3^rd, 2007, 12:26am By: trond
How to break in a "case ...endcase" statement ??	ZaraCattle	6	5032	Apr 30^th, 2007, 4:21am By: Geoffrey_Coram
implement laplace_zp function from measurements	Pavel	2	4799	Apr 26^th, 2007, 3:15am By: Pavel
Moved: How to compile a file Simulation.v ? - Started by: Forum Administrator This Topic has been moved to Logic Simulators by Forum Administrator.
what kind of verilg-A model need for a PLL AC sim?	bluestatic	8	6803	Apr 19^th, 2007, 9:50pm By: calven
parameter array declaration error	Pavel	5	92	Apr 19^th, 2007, 5:24am By: Geoffrey_Coram
error when adding 2 variables	Pavel	2	2097	Apr 17^th, 2007, 1:04am By: Pavel

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