I have a few general questions concerning the selection of analog simulation analyses for PLL design.  I have simulated my VCO, PFD, and Frequency divider blocks individually with transient and PSS analyses.  However, I run into problems when attempting to run a system level PSS analysis.  I assume this is due to the presence of the VCO which will produce frequencies that are non-integer multiples of the fundamental frequency.  Can PSS analysis be used to find the steady state input voltage to the VCO in a full PLL model?  Or is this value only determined through lengthy transient analyses?  I'm assuming that the phase and jitter noise of the system will be determined by performing PSS followed by Pnoise, etc. for the individual blocks and building a phase domain model based on the results (per Ken's paper).  Thanks,

Dan